-#include "decode.h"
-#include "trap.h"
-#include "icsim.h"
-#include <assert.h>
+// See LICENSE for license details.
-class processor_t;
+#ifndef _RISCV_MMU_H
+#define _RISCV_MMU_H
-const reg_t LEVELS = 4;
-const reg_t PGSHIFT = 12;
+#include "decode.h"
+#include "trap.h"
+#include "common.h"
+#include "config.h"
+#include "processor.h"
+#include "memtracer.h"
+#include <vector>
+
+// virtual memory configuration
+typedef reg_t pte_t;
+const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2;
+const reg_t PGSHIFT = 13;
const reg_t PGSIZE = 1 << PGSHIFT;
+const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
+const reg_t VPN_BITS = PTIDXBITS * LEVELS;
const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
-
-struct pte_t
-{
- reg_t t : 1;
- reg_t e : 1;
- reg_t r : 1;
- reg_t d : 1;
- reg_t ux : 1;
- reg_t uw : 1;
- reg_t ur : 1;
- reg_t sx : 1;
- reg_t sw : 1;
- reg_t sr : 1;
- reg_t unused1 : 2;
- reg_t ppn : PPN_BITS;
-};
-
+const reg_t VA_BITS = VPN_BITS + PGSHIFT;
+
+// page table entry (PTE) fields
+#define PTE_T 0x001 // Entry is a page Table descriptor
+#define PTE_E 0x002 // Entry is a page table Entry
+#define PTE_R 0x004 // Referenced
+#define PTE_D 0x008 // Dirty
+#define PTE_UX 0x010 // User eXecute permission
+#define PTE_UW 0x020 // User Read permission
+#define PTE_UR 0x040 // User Write permission
+#define PTE_SX 0x080 // Supervisor eXecute permission
+#define PTE_SW 0x100 // Supervisor Read permission
+#define PTE_SR 0x200 // Supervisor Write permission
+#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
+#define PTE_PPN_SHIFT 13 // LSB of physical page number in the PTE
+
+// this class implements a processor's port into the virtual memory system.
+// an MMU and instruction cache are maintained for simulator performance.
class mmu_t
{
public:
- mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), badvaddr(0),
- ptbr(0), supervisor(true), vm_enabled(false),
- icsim(NULL), dcsim(NULL), itlbsim(NULL), dtlbsim(NULL)
- {
- }
-
- #ifdef RISCV_ENABLE_ICSIM
- # define dcsim_tick(dcsim, dtlbsim, addr, size, st) \
- do { if(dcsim) (dcsim)->tick(addr, size, st); \
- if(dtlbsim) (dtlbsim)->tick(addr, sizeof(reg_t), false); } while(0)
- #else
- # define dcsim_tick(dcsim, dtlbsim, addr, size, st)
- #endif
+ mmu_t(char* _mem, size_t _memsz);
+ ~mmu_t();
+ // template for functions that load an aligned value from memory
#define load_func(type) \
type##_t load_##type(reg_t addr) { \
- check_align(addr, sizeof(type##_t), false, false); \
- addr = translate(addr, false, false); \
- dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), false); \
- return *(type##_t*)(mem+addr); \
+ if(unlikely(addr % sizeof(type##_t))) \
+ { \
+ badvaddr = addr; \
+ throw trap_load_address_misaligned; \
+ } \
+ reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
+ return *(type##_t*)(mem + paddr); \
+ } \
+ type##_t load_reserved_##type(reg_t addr) { \
+ load_reservation = addr; \
+ return load_##type(addr); \
}
+ // load value from memory at aligned address; zero extend to register width
+ load_func(uint8)
+ load_func(uint16)
+ load_func(uint32)
+ load_func(uint64)
+
+ // load value from memory at aligned address; sign extend to register width
+ load_func(int8)
+ load_func(int16)
+ load_func(int32)
+ load_func(int64)
+
+ // template for functions that store an aligned value to memory
#define store_func(type) \
void store_##type(reg_t addr, type##_t val) { \
- check_align(addr, sizeof(type##_t), true, false); \
- addr = translate(addr, true, false); \
- dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), true); \
- *(type##_t*)(mem+addr) = val; \
+ if(unlikely(addr % sizeof(type##_t))) \
+ { \
+ badvaddr = addr; \
+ throw trap_store_address_misaligned; \
+ } \
+ reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
+ *(type##_t*)(mem + paddr) = val; \
+ } \
+ reg_t store_conditional_##type(reg_t addr, type##_t val) { \
+ if (addr == load_reservation) { \
+ store_##type(addr, val); \
+ return 0; \
+ } else return 1; \
}
- insn_t load_insn(reg_t addr, bool rvc)
+ // store value to memory at aligned address
+ store_func(uint8)
+ store_func(uint16)
+ store_func(uint32)
+ store_func(uint64)
+
+ struct insn_fetch_t
{
insn_t insn;
-
- reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
- if(addr % 4 == 0 && icache_tag[idx] == (addr | 1))
- return icache_data[idx];
-
+ insn_func_t func;
+ };
+
+ // load instruction from memory at aligned address.
+ // (needed because instruction alignment requirement is variable
+ // if RVC is supported)
+ // returns the instruction at the specified address, given the current
+ // RVC mode. func is set to a pointer to a function that knows how to
+ // execute the returned instruction.
+ inline insn_fetch_t load_insn(reg_t addr, bool rvc)
+ {
#ifdef RISCV_ENABLE_RVC
- if(addr % 4 == 2 && rvc)
+ if(addr % 4 == 2 && rvc) // fetch across word boundary
{
- reg_t paddr_lo = translate(addr, false, true);
- insn.bits = *(uint16_t*)(mem+paddr_lo);
+ reg_t addr_lo = translate(addr, 2, false, true);
+ insn_fetch_t fetch;
+ fetch.insn.bits = *(uint16_t*)(mem + addr_lo);
+ fetch.func = get_insn_func(fetch.insn, sr);
- if(!INSN_IS_RVC(insn.bits))
+ if(!INSN_IS_RVC(fetch.insn.bits))
{
- reg_t paddr_hi = translate(addr+2, false, true);
- insn.bits |= (uint32_t)*(uint16_t*)(mem+paddr_hi) << 16;
+ reg_t addr_hi = translate(addr+2, 2, false, true);
+ fetch.insn.bits |= (uint32_t)*(uint16_t*)(mem + addr_hi) << 16;
}
+ return fetch;
}
else
#endif
{
- check_align(addr, 4, false, true);
- reg_t paddr = translate(addr, false, true);
- insn = *(insn_t*)(mem+paddr);
+ reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
+ insn_fetch_t fetch;
+ if (unlikely(icache_tag[idx] != addr))
+ {
+ reg_t paddr = translate(addr, sizeof(insn_t), false, true);
+ fetch.insn = *(insn_t*)(mem + paddr);
+ fetch.func = get_insn_func(fetch.insn, sr);
- icache_tag[idx] = addr | 1;
- icache_data[idx] = insn;
- }
+ reg_t idx = (paddr/sizeof(insn_t)) % ICACHE_ENTRIES;
+ icache_tag[idx] = addr;
+ icache_data[idx] = fetch.insn;
+ icache_func[idx] = fetch.func;
- #ifdef RISCV_ENABLE_ICSIM
- if(icsim)
- icsim->tick(addr, insn_length(insn), false);
- if(itlbsim)
- itlbsim->tick(addr, sizeof(reg_t), false);
- #endif
-
- return insn;
+ if (tracer.interested_in_range(paddr, paddr + sizeof(insn_t), false, true))
+ {
+ icache_tag[idx] = -1;
+ tracer.trace(paddr, sizeof(insn_t), false, true);
+ }
+ }
+ fetch.insn = icache_data[idx];;
+ fetch.func = icache_func[idx];
+ return fetch;
+ }
}
- load_func(uint8)
- load_func(uint16)
- load_func(uint32)
- load_func(uint64)
-
- load_func(int8)
- load_func(int16)
- load_func(int32)
- load_func(int64)
-
- store_func(uint8)
- store_func(uint16)
- store_func(uint32)
- store_func(uint64)
-
+ // get the virtual address that caused a fault
reg_t get_badvaddr() { return badvaddr; }
- reg_t get_ptbr() { return ptbr; }
- void set_supervisor(bool sup) { supervisor = sup; }
- void set_vm_enabled(bool en) { vm_enabled = en; }
+ // get/set the page table base register
+ reg_t get_ptbr() { return ptbr; }
void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
+ void yield_load_reservation() { load_reservation = -1; }
+ void set_sr(uint32_t sr); // keep the MMU in sync with the processor mode
- void set_icsim(icsim_t* _icsim) { icsim = _icsim; }
- void set_dcsim(icsim_t* _dcsim) { dcsim = _dcsim; }
- void set_itlbsim(icsim_t* _itlbsim) { itlbsim = _itlbsim; }
- void set_dtlbsim(icsim_t* _dtlbsim) { dtlbsim = _dtlbsim; }
-
+ // flush the TLB and instruction cache
void flush_tlb();
void flush_icache();
+ void register_memtracer(memtracer_t*);
+
private:
char* mem;
size_t memsz;
+ reg_t load_reservation;
reg_t badvaddr;
-
reg_t ptbr;
- bool supervisor;
- bool vm_enabled;
-
- static const reg_t TLB_ENTRIES = 32;
- pte_t tlb_data[TLB_ENTRIES];
- reg_t tlb_tag[TLB_ENTRIES];
-
- static const reg_t ICACHE_ENTRIES = 32;
+ uint32_t sr;
+ memtracer_list_t tracer;
+
+ // implement a TLB for simulator performance
+ static const reg_t TLB_ENTRIES = 256;
+ reg_t tlb_data[TLB_ENTRIES];
+ reg_t tlb_insn_tag[TLB_ENTRIES];
+ reg_t tlb_load_tag[TLB_ENTRIES];
+ reg_t tlb_store_tag[TLB_ENTRIES];
+
+ // implement an instruction cache for simulator performance
+ static const reg_t ICACHE_ENTRIES = 256;
insn_t icache_data[ICACHE_ENTRIES];
+ insn_func_t icache_func[ICACHE_ENTRIES];
reg_t icache_tag[ICACHE_ENTRIES];
- icsim_t* icsim;
- icsim_t* dcsim;
- icsim_t* itlbsim;
- icsim_t* dtlbsim;
+ // finish translation on a TLB miss and upate the TLB
+ reg_t refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
- void check_align(reg_t addr, int size, bool store, bool fetch)
- {
- if(addr & (size-1))
- {
- badvaddr = addr;
- if(fetch)
- throw trap_instruction_address_misaligned;
- if(store)
- throw trap_store_address_misaligned;
- throw trap_load_address_misaligned;
- }
- }
+ // perform a page table walk for a given virtual address
+ pte_t walk(reg_t addr);
- reg_t translate(reg_t addr, bool store, bool fetch)
+ // translate a virtual address to a physical address
+ reg_t translate(reg_t addr, reg_t bytes, bool store, bool fetch)
{
reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
- pte_t pte = tlb_data[idx];
- reg_t tag = tlb_tag[idx];
-
- trap_t trap = store ? trap_store_access_fault
- : fetch ? trap_instruction_access_fault
- : trap_load_access_fault;
-
- if(!pte.e || tag != (addr >> PGSHIFT))
- {
- pte = walk(addr);
- if(!pte.e)
- throw trap;
-
- tlb_data[idx] = pte;
- tlb_tag[idx] = addr >> PGSHIFT;
- }
-
- if(store && !(supervisor ? pte.sw : pte.uw) ||
- !store && !fetch && !(supervisor ? pte.sr : pte.ur) ||
- !store && !fetch && !(supervisor ? pte.sr : pte.ur))
- throw trap;
- return (addr & (PGSIZE-1)) | (pte.ppn << PGSHIFT);
- }
+ reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
+ reg_t expected_tag = addr & ~(PGSIZE-1);
+ if(likely(tlb_tag[idx] == expected_tag))
+ return ((uintptr_t)addr & (PGSIZE-1)) + tlb_data[idx];
- pte_t walk(reg_t addr)
- {
- pte_t pte;
-
- if(!vm_enabled)
- {
- pte.t = 0;
- pte.e = addr < memsz;
- pte.r = pte.d = 0;
- pte.ur = pte.uw = pte.ux = pte.sr = pte.sw = pte.sx = 1;
- pte.ppn = addr >> PGSHIFT;
- }
- else
- {
- pte.t = pte.e = 0;
-
- int lg_ptesz = sizeof(pte_t) == 4 ? 2
- : sizeof(pte_t) == 8 ? 3
- : 0;
- assert(lg_ptesz);
-
- reg_t base = ptbr;
-
- for(int i = LEVELS-1; i >= 0; i--)
- {
- int idxbits = PGSHIFT - lg_ptesz;
- int shift = PGSHIFT + i*idxbits;
- reg_t idx = addr >> shift;
- idx &= (1 << idxbits) - 1;
-
- reg_t pte_addr = base + idx*sizeof(pte_t);
- if(pte_addr >= memsz)
- break;
-
- pte = *(pte_t*)(mem+pte_addr);
- if(pte.e)
- {
- // if this PTE is from a larger PT, fake a leaf
- // PTE so the TLB will work right
- reg_t vpn = addr >> PGSHIFT;
- pte.ppn += vpn & ((1<<(i*idxbits))-1);
- break;
- }
- if(!pte.t)
- break;
-
- base = pte.ppn << PGSHIFT;
- }
- }
-
- return pte;
+ return refill_tlb(addr, bytes, store, fetch);
}
friend class processor_t;
};
+
+#endif
projects / riscv-isa-sim.git / blobdiff