add load-reserved/store-conditional instructions

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index b2a48e6f3b0d94375823a3ea5cf5a0bf41615c42..a5d150f8e5a4ceed9cdf76d1527cdd9f0216505b 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_MMU_H
 #define _RISCV_MMU_H
 
@@ -9,8 +11,6 @@
 #include "memtracer.h"
 #include <vector>
 
-class processor_t;
-
 // virtual memory configuration
 typedef reg_t pte_t;
 const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2;
@@ -53,6 +53,10 @@ public:
       } \
       reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
       return *(type##_t*)(mem + paddr); \
+    } \
+    type##_t load_reserved_##type(reg_t addr) { \
+      load_reservation = addr; \
+      return load_##type(addr); \
     }
 
   // load value from memory at aligned address; zero extend to register width
@@ -77,6 +81,12 @@ public:
       } \
       reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
       *(type##_t*)(mem + paddr) = val; \
+    } \
+    reg_t store_conditional_##type(reg_t addr, type##_t val) { \
+      if (addr == load_reservation) { \
+        store_##type(addr, val); \
+        return 0; \
+      } else return 1; \
     }
 
   // store value to memory at aligned address
@@ -105,8 +115,7 @@ public:
       reg_t addr_lo = translate(addr, 2, false, true);
       insn_fetch_t fetch;
       fetch.insn.bits = *(uint16_t*)(mem + addr_lo);
-      size_t dispatch_idx = fetch.insn.bits % processor_t::DISPATCH_TABLE_SIZE;
-      fetch.func = processor_t::dispatch_table[dispatch_idx];
+      fetch.func = get_insn_func(fetch.insn, sr);
 
       if(!INSN_IS_RVC(fetch.insn.bits))
       {
@@ -124,8 +133,7 @@ public:
       {
         reg_t paddr = translate(addr, sizeof(insn_t), false, true);
         fetch.insn = *(insn_t*)(mem + paddr);
-        size_t dispatch_idx = fetch.insn.bits % processor_t::DISPATCH_TABLE_SIZE;
-        fetch.func = processor_t::dispatch_table[dispatch_idx];
+        fetch.func = get_insn_func(fetch.insn, sr);
 
         reg_t idx = (paddr/sizeof(insn_t)) % ICACHE_ENTRIES;
         icache_tag[idx] = addr;
@@ -150,10 +158,8 @@ public:
   // get/set the page table base register
   reg_t get_ptbr() { return ptbr; }
   void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
-
-  // keep the MMU in sync with processor mode
-  void set_supervisor(bool sup) { supervisor = sup; }
-  void set_vm_enabled(bool en) { vm_enabled = en; }
+  void yield_load_reservation() { load_reservation = -1; }
+  void set_sr(uint32_t sr); // keep the MMU in sync with the processor mode
 
   // flush the TLB and instruction cache
   void flush_tlb();
@@ -164,10 +170,10 @@ public:
 private:
   char* mem;
   size_t memsz;
+  reg_t load_reservation;
   reg_t badvaddr;
   reg_t ptbr;
-  bool supervisor;
-  bool vm_enabled;
+  uint32_t sr;
   memtracer_list_t tracer;
 
   // implement a TLB for simulator performance