#include "config.h"
#include "processor.h"
#include "memtracer.h"
+#include <stdlib.h>
#include <vector>
// virtual memory configuration
-typedef reg_t pte_t;
-const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
-const reg_t PTIDXBITS = 10;
-const reg_t PGSHIFT = PTIDXBITS + (sizeof(pte_t) == 8 ? 3 : 2);
+#define PGSHIFT 12
const reg_t PGSIZE = 1 << PGSHIFT;
-const reg_t VPN_BITS = PTIDXBITS * LEVELS;
-const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
-const reg_t VA_BITS = VPN_BITS + PGSHIFT;
+
+struct insn_fetch_t
+{
+ insn_func_t func;
+ insn_t insn;
+};
+
+struct icache_entry_t {
+ reg_t tag;
+ reg_t pad;
+ insn_fetch_t data;
+};
// this class implements a processor's port into the virtual memory system.
// an MMU and instruction cache are maintained for simulator performance.
// template for functions that load an aligned value from memory
#define load_func(type) \
- type##_t load_##type(reg_t addr) { \
- if(unlikely(addr % sizeof(type##_t))) \
- { \
- badvaddr = addr; \
- throw trap_load_address_misaligned; \
- } \
- reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
- return *(type##_t*)(mem + paddr); \
- } \
- type##_t load_reserved_##type(reg_t addr) { \
- load_reservation = addr; \
- return load_##type(addr); \
+ type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
+ if (addr & (sizeof(type##_t)-1)) \
+ throw trap_load_address_misaligned(addr); \
+ reg_t vpn = addr >> PGSHIFT; \
+ if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) \
+ return *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr); \
+ type##_t res; \
+ load_slow_path(addr, sizeof(type##_t), (uint8_t*)&res); \
+ return res; \
}
// load value from memory at aligned address; zero extend to register width
// template for functions that store an aligned value to memory
#define store_func(type) \
void store_##type(reg_t addr, type##_t val) { \
- if(unlikely(addr % sizeof(type##_t))) \
- { \
- badvaddr = addr; \
- throw trap_store_address_misaligned; \
- } \
- reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
- *(type##_t*)(mem + paddr) = val; \
- } \
- reg_t store_conditional_##type(reg_t addr, type##_t val) { \
- if (addr == load_reservation) { \
- store_##type(addr, val); \
- return 0; \
- } else return 1; \
+ if (addr & (sizeof(type##_t)-1)) \
+ throw trap_store_address_misaligned(addr); \
+ reg_t vpn = addr >> PGSHIFT; \
+ if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
+ *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
+ else \
+ store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \
}
// store value to memory at aligned address
store_func(uint32)
store_func(uint64)
- struct insn_fetch_t
+ static const reg_t ICACHE_ENTRIES = 1024;
+
+ inline size_t icache_index(reg_t addr)
{
- insn_func_t func;
- insn_t insn;
- };
+ return (addr / PC_ALIGN) % ICACHE_ENTRIES;
+ }
- // load instruction from memory at aligned address.
- inline insn_fetch_t load_insn(reg_t addr)
+ inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry)
{
- reg_t idx = (addr/sizeof(insn_t::itype)) % ICACHE_ENTRIES;
- if (unlikely(icache_tag[idx] != addr))
- {
- reg_t paddr = translate(addr, sizeof(insn_t::itype), false, true);
- insn_fetch_t fetch;
- fetch.insn.itype = *(decltype(insn_t::itype)*)(mem + paddr);
- fetch.func = proc->decode_insn(fetch.insn);
-
- reg_t idx = (paddr/sizeof(insn_t::itype)) % ICACHE_ENTRIES;
- icache_tag[idx] = addr;
- icache_data[idx] = fetch;
-
- if (tracer.interested_in_range(paddr, paddr + sizeof(insn_t::itype), false, true))
- {
- icache_tag[idx] = -1;
- tracer.trace(paddr, sizeof(insn_t::itype), false, true);
- }
+ const uint16_t* iaddr = translate_insn_addr(addr);
+ insn_bits_t insn = *iaddr;
+ int length = insn_length(insn);
+
+ if (likely(length == 4)) {
+ if (likely(addr % PGSIZE < PGSIZE-2))
+ insn |= (insn_bits_t)*(const int16_t*)(iaddr + 1) << 16;
+ else
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 2) << 16;
+ } else if (length == 2) {
+ insn = (int16_t)insn;
+ } else if (length == 6) {
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 4) << 32;
+ insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 2) << 16;
+ } else {
+ static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t");
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 6) << 48;
+ insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 4) << 32;
+ insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 2) << 16;
+ }
+
+ insn_fetch_t fetch = {proc->decode_insn(insn), insn};
+ entry->tag = addr;
+ entry->data = fetch;
+
+ reg_t paddr = (const char*)iaddr - mem;
+ if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) {
+ entry->tag = -1;
+ tracer.trace(paddr, length, FETCH);
}
- return icache_data[idx];
+ return entry;
+ }
+
+ inline icache_entry_t* access_icache(reg_t addr)
+ {
+ icache_entry_t* entry = &icache[icache_index(addr)];
+ if (likely(entry->tag == addr))
+ return entry;
+ return refill_icache(addr, entry);
+ }
+
+ inline insn_fetch_t load_insn(reg_t addr)
+ {
+ return access_icache(addr)->data;
}
- reg_t get_badvaddr() { return badvaddr; }
- reg_t get_ptbr() { return ptbr; }
- void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
void set_processor(processor_t* p) { proc = p; flush_tlb(); }
void flush_tlb();
void flush_icache();
- void yield_load_reservation() { load_reservation = -1; }
void register_memtracer(memtracer_t*);
private:
char* mem;
size_t memsz;
- reg_t load_reservation;
- reg_t badvaddr;
- reg_t ptbr;
processor_t* proc;
memtracer_list_t tracer;
// implement an instruction cache for simulator performance
- static const reg_t ICACHE_ENTRIES = 256;
- insn_fetch_t icache_data[ICACHE_ENTRIES];
+ icache_entry_t icache[ICACHE_ENTRIES];
// implement a TLB for simulator performance
static const reg_t TLB_ENTRIES = 256;
- reg_t tlb_data[TLB_ENTRIES];
+ char* tlb_data[TLB_ENTRIES];
reg_t tlb_insn_tag[TLB_ENTRIES];
reg_t tlb_load_tag[TLB_ENTRIES];
reg_t tlb_store_tag[TLB_ENTRIES];
- reg_t icache_tag[ICACHE_ENTRIES];
// finish translation on a TLB miss and upate the TLB
- reg_t refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
-
- // perform a page table walk for a given virtual address
- pte_t walk(reg_t addr);
-
- // translate a virtual address to a physical address
- reg_t translate(reg_t addr, reg_t bytes, bool store, bool fetch)
- {
- reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
-
- reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
- reg_t expected_tag = addr & ~(PGSIZE-1);
- if(likely(tlb_tag[idx] == expected_tag))
- return ((uintptr_t)addr & (PGSIZE-1)) + tlb_data[idx];
-
- return refill_tlb(addr, bytes, store, fetch);
+ void refill_tlb(reg_t vaddr, reg_t paddr, access_type type);
+
+ // perform a page table walk for a given VA; set referenced/dirty bits
+ reg_t walk(reg_t addr, bool supervisor, access_type type);
+
+ // handle uncommon cases: TLB misses, page faults, MMIO
+ const uint16_t* fetch_slow_path(reg_t addr);
+ void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes);
+ void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes);
+ reg_t translate(reg_t addr, access_type type);
+
+ // ITLB lookup
+ const uint16_t* translate_insn_addr(reg_t addr) __attribute__((always_inline)) {
+ reg_t vpn = addr >> PGSHIFT;
+ if (likely(tlb_insn_tag[vpn % TLB_ENTRIES] == vpn))
+ return (uint16_t*)(tlb_data[vpn % TLB_ENTRIES] + addr);
+ return fetch_slow_path(addr);
}
friend class processor_t;
projects / riscv-isa-sim.git / blobdiff