Instructions are no longer member functions

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 64b11d3b31ff440d588ea84ccc7937160777de02..b69de9c9020670f29e63e0bc78c5e82d8f7163b4 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -13,28 +13,14 @@
 
 // virtual memory configuration
 typedef reg_t pte_t;
-const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2;
-const reg_t PGSHIFT = 13;
+const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
+const reg_t PTIDXBITS = 10;
+const reg_t PGSHIFT = PTIDXBITS + (sizeof(pte_t) == 8 ? 3 : 2);
 const reg_t PGSIZE = 1 << PGSHIFT;
-const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
 const reg_t VPN_BITS = PTIDXBITS * LEVELS;
 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
 const reg_t VA_BITS = VPN_BITS + PGSHIFT;
 
-// page table entry (PTE) fields
-#define PTE_T    0x001 // Entry is a page Table descriptor
-#define PTE_E    0x002 // Entry is a page table Entry
-#define PTE_R    0x004 // Referenced
-#define PTE_D    0x008 // Dirty
-#define PTE_UX   0x010 // User eXecute permission
-#define PTE_UW   0x020 // User Read permission
-#define PTE_UR   0x040 // User Write permission
-#define PTE_SX   0x080 // Supervisor eXecute permission
-#define PTE_SW   0x100 // Supervisor Read permission
-#define PTE_SR   0x200 // Supervisor Write permission
-#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
-#define PTE_PPN_SHIFT  13 // LSB of physical page number in the PTE
-
 // this class implements a processor's port into the virtual memory system.
 // an MMU and instruction cache are maintained for simulator performance.
 class mmu_t
@@ -47,16 +33,9 @@ public:
   #define load_func(type) \
     type##_t load_##type(reg_t addr) { \
       if(unlikely(addr % sizeof(type##_t))) \
-      { \
-        badvaddr = addr; \
-        throw trap_load_address_misaligned; \
-      } \
+        throw trap_load_address_misaligned(addr); \
       reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
       return *(type##_t*)(mem + paddr); \
-    } \
-    type##_t load_reserved_##type(reg_t addr) { \
-      load_reservation = addr; \
-      return load_##type(addr); \
     }
 
   // load value from memory at aligned address; zero extend to register width
@@ -75,18 +54,9 @@ public:
   #define store_func(type) \
     void store_##type(reg_t addr, type##_t val) { \
       if(unlikely(addr % sizeof(type##_t))) \
-      { \
-        badvaddr = addr; \
-        throw trap_store_address_misaligned; \
-      } \
+        throw trap_store_address_misaligned(addr); \
       reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
       *(type##_t*)(mem + paddr) = val; \
-    } \
-    reg_t store_conditional_##type(reg_t addr, type##_t val) { \
-      if (addr == load_reservation) { \
-        store_##type(addr, val); \
-        return 0; \
-      } else return 1; \
     }
 
   // store value to memory at aligned address
@@ -125,23 +95,16 @@ public:
     return icache_data[idx];
   }
 
-  reg_t get_badvaddr() { return badvaddr; }
-  reg_t get_ptbr() { return ptbr; }
-  void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
   void set_processor(processor_t* p) { proc = p; flush_tlb(); }
 
   void flush_tlb();
   void flush_icache();
-  void yield_load_reservation() { load_reservation = -1; }
 
   void register_memtracer(memtracer_t*);
 
 private:
   char* mem;
   size_t memsz;
-  reg_t load_reservation;
-  reg_t badvaddr;
-  reg_t ptbr;
   processor_t* proc;
   memtracer_list_t tracer;