+// See LICENSE for license details.
+
#ifndef _RISCV_MMU_H
#define _RISCV_MMU_H
#include "decode.h"
+#include "icache.h"
#include "trap.h"
#include "common.h"
#include "config.h"
#include "memtracer.h"
#include <vector>
-class processor_t;
-
// virtual memory configuration
typedef reg_t pte_t;
-const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2;
-const reg_t PGSHIFT = 13;
+const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
+const reg_t PTIDXBITS = 10;
+const reg_t PGSHIFT = PTIDXBITS + (sizeof(pte_t) == 8 ? 3 : 2);
const reg_t PGSIZE = 1 << PGSHIFT;
-const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
const reg_t VPN_BITS = PTIDXBITS * LEVELS;
const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
const reg_t VA_BITS = VPN_BITS + PGSHIFT;
-// page table entry (PTE) fields
-#define PTE_T 0x001 // Entry is a page Table descriptor
-#define PTE_E 0x002 // Entry is a page table Entry
-#define PTE_R 0x004 // Referenced
-#define PTE_D 0x008 // Dirty
-#define PTE_UX 0x010 // User eXecute permission
-#define PTE_UW 0x020 // User Read permission
-#define PTE_UR 0x040 // User Write permission
-#define PTE_SX 0x080 // Supervisor eXecute permission
-#define PTE_SW 0x100 // Supervisor Read permission
-#define PTE_SR 0x200 // Supervisor Write permission
-#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
-#define PTE_PPN_SHIFT 13 // LSB of physical page number in the PTE
+struct insn_fetch_t
+{
+ insn_func_t func;
+ union {
+ insn_t insn;
+ uint_fast32_t pad;
+ } insn;
+};
+
+struct icache_entry_t {
+ reg_t tag;
+ reg_t pad;
+ insn_fetch_t data;
+};
// this class implements a processor's port into the virtual memory system.
// an MMU and instruction cache are maintained for simulator performance.
// template for functions that load an aligned value from memory
#define load_func(type) \
- type##_t load_##type(reg_t addr) { \
- if(unlikely(addr % sizeof(type##_t))) \
- { \
- badvaddr = addr; \
- throw trap_load_address_misaligned; \
- } \
- reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
- return *(type##_t*)(mem + paddr); \
+ type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
+ void* paddr = translate(addr, sizeof(type##_t), false, false); \
+ return *(type##_t*)paddr; \
}
// load value from memory at aligned address; zero extend to register width
// template for functions that store an aligned value to memory
#define store_func(type) \
void store_##type(reg_t addr, type##_t val) { \
- if(unlikely(addr % sizeof(type##_t))) \
- { \
- badvaddr = addr; \
- throw trap_store_address_misaligned; \
- } \
- reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
- *(type##_t*)(mem + paddr) = val; \
+ void* paddr = translate(addr, sizeof(type##_t), true, false); \
+ *(type##_t*)paddr = val; \
}
// store value to memory at aligned address
store_func(uint32)
store_func(uint64)
- struct insn_fetch_t
- {
- insn_t insn;
- insn_func_t func;
- };
-
// load instruction from memory at aligned address.
- // (needed because instruction alignment requirement is variable
- // if RVC is supported)
- // returns the instruction at the specified address, given the current
- // RVC mode. func is set to a pointer to a function that knows how to
- // execute the returned instruction.
- inline insn_fetch_t load_insn(reg_t addr, bool rvc)
+ inline icache_entry_t* access_icache(reg_t addr)
{
- #ifdef RISCV_ENABLE_RVC
- if(addr % 4 == 2 && rvc) // fetch across word boundary
- {
- reg_t addr_lo = translate(addr, 2, false, true);
- insn_fetch_t fetch;
- fetch.insn.bits = *(uint16_t*)(mem + addr_lo);
- size_t dispatch_idx = fetch.insn.bits % processor_t::DISPATCH_TABLE_SIZE;
- fetch.func = processor_t::dispatch_table[dispatch_idx];
-
- if(!INSN_IS_RVC(fetch.insn.bits))
- {
- reg_t addr_hi = translate(addr+2, 2, false, true);
- fetch.insn.bits |= (uint32_t)*(uint16_t*)(mem + addr_hi) << 16;
- }
- return fetch;
- }
- else
- #endif
+ reg_t idx = (addr / sizeof(insn_t)) % ICACHE_SIZE;
+ icache_entry_t* entry = &icache[idx];
+ if (likely(entry->tag == addr))
+ return entry;
+
+ void* iaddr = translate(addr, sizeof(insn_t), false, true);
+ insn_fetch_t fetch;
+ fetch.insn.pad = *(decltype(fetch.insn.insn.bits())*)iaddr;
+ fetch.func = proc->decode_insn(fetch.insn.insn);
+
+ icache[idx].tag = addr;
+ icache[idx].data = fetch;
+
+ reg_t paddr = (char*)iaddr - mem;
+ if (!tracer.empty() && tracer.interested_in_range(paddr, paddr + sizeof(insn_t), false, true))
{
- reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
- insn_fetch_t fetch;
- if (unlikely(icache_tag[idx] != addr))
- {
- reg_t paddr = translate(addr, sizeof(insn_t), false, true);
- fetch.insn = *(insn_t*)(mem + paddr);
- size_t dispatch_idx = fetch.insn.bits % processor_t::DISPATCH_TABLE_SIZE;
- fetch.func = processor_t::dispatch_table[dispatch_idx];
-
- reg_t idx = (paddr/sizeof(insn_t)) % ICACHE_ENTRIES;
- icache_tag[idx] = addr;
- icache_data[idx] = fetch.insn;
- icache_func[idx] = fetch.func;
-
- if (tracer.interested_in_range(paddr, paddr + sizeof(insn_t), false, true))
- {
- icache_tag[idx] = -1;
- tracer.trace(paddr, sizeof(insn_t), false, true);
- }
- }
- fetch.insn = icache_data[idx];;
- fetch.func = icache_func[idx];
- return fetch;
+ icache[idx].tag = -1;
+ tracer.trace(paddr, sizeof(insn_t), false, true);
}
+ return &icache[idx];
}
- // get the virtual address that caused a fault
- reg_t get_badvaddr() { return badvaddr; }
-
- // get/set the page table base register
- reg_t get_ptbr() { return ptbr; }
- void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
+ inline insn_fetch_t load_insn(reg_t addr)
+ {
+ return access_icache(addr)->data;
+ }
- // keep the MMU in sync with processor mode
- void set_supervisor(bool sup) { supervisor = sup; }
- void set_vm_enabled(bool en) { vm_enabled = en; }
+ void set_processor(processor_t* p) { proc = p; flush_tlb(); }
- // flush the TLB and instruction cache
void flush_tlb();
void flush_icache();
private:
char* mem;
size_t memsz;
- reg_t badvaddr;
- reg_t ptbr;
- bool supervisor;
- bool vm_enabled;
+ processor_t* proc;
memtracer_list_t tracer;
+ // implement an instruction cache for simulator performance
+ icache_entry_t icache[ICACHE_SIZE];
+
// implement a TLB for simulator performance
static const reg_t TLB_ENTRIES = 256;
- reg_t tlb_data[TLB_ENTRIES];
+ char* tlb_data[TLB_ENTRIES];
reg_t tlb_insn_tag[TLB_ENTRIES];
reg_t tlb_load_tag[TLB_ENTRIES];
reg_t tlb_store_tag[TLB_ENTRIES];
- // implement an instruction cache for simulator performance
- static const reg_t ICACHE_ENTRIES = 256;
- insn_t icache_data[ICACHE_ENTRIES];
- insn_func_t icache_func[ICACHE_ENTRIES];
- reg_t icache_tag[ICACHE_ENTRIES];
-
// finish translation on a TLB miss and upate the TLB
- reg_t refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
+ void* refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
// perform a page table walk for a given virtual address
pte_t walk(reg_t addr);
// translate a virtual address to a physical address
- reg_t translate(reg_t addr, reg_t bytes, bool store, bool fetch)
+ void* translate(reg_t addr, reg_t bytes, bool store, bool fetch)
+ __attribute__((always_inline))
{
reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
+ reg_t expected_tag = addr >> PGSHIFT;
+ reg_t* tags = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
+ reg_t tag = tags[idx];
+ void* data = tlb_data[idx] + addr;
+
+ if (unlikely(addr & (bytes-1)))
+ store ? throw trap_store_address_misaligned(addr) : throw trap_load_address_misaligned(addr);
- reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
- reg_t expected_tag = addr & ~(PGSIZE-1);
- if(likely(tlb_tag[idx] == expected_tag))
- return ((uintptr_t)addr & (PGSIZE-1)) + tlb_data[idx];
+ if (likely(tag == expected_tag))
+ return data;
return refill_tlb(addr, bytes, store, fetch);
}
projects / riscv-isa-sim.git / blobdiff