add SUBVL CSR set

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 19ebffcb26c2174f58611da2961463bc4c78350e..09467bc3b164887c33e017563a90ded7352f2437 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -539,6 +539,12 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       }
       break;
     }
+    case CSR_USVSUBVL:
+      state.sv().subvl = std::max(1, std::min(4, (int)val));
+      old_val = state.sv().subvl;
+      // TODO XXX throw exception if val attempted to be set == 0
+      fprintf(stderr, "set VL %lx\n", state.sv().vl);
+      break;
     case CSR_USVVL:
       state.sv().vl = std::min(state.sv().mvl, val + 1);
       old_val = state.sv().mvl - 1;