printf wrong args

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index fcfdb6d8b00dbe88796fd196f6d0a865df4c482f..1b75e1361271f5b3f90874409622e1b22ef8ffaa 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -902,7 +902,7 @@ reg_t processor_t::get_csr(int which)
     case CSR_SV_CFG:
       return (state.sv().state_bank)      | (state.sv().state_size<<3);
     case CSR_SV_STATE:
-      fprintf(stderr, "get CSR_SV_STATE vl %d mvl %d subvl %d\n",
+      fprintf(stderr, "get CSR_SV_STATE vl %ld mvl %ld subvl %ld\n",
                             state.sv().vl,
                             state.sv().mvl,
                             state.sv().subvl);