initialise SUBVL to 1

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c93c2e52329c899c9bdbee7927cc877ebe9c7cfd..581c54964ad6b5140749f16e4e1b9b0785d576db 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -143,6 +143,14 @@ void state_t::reset(reg_t max_isa)
   msv.state_size = 1;
   ssv.state_size = 1;
   usv.state_size = 3;
+  // VL and MVL all 0
+  msv.vl = msv.mvl = 0;
+  ssv.vl = ssv.mvl = 0;
+  usv.vl = usv.mvl = 0;
+  // SUBVL all 1
+  msv.subvl = 1;
+  ssv.subvl = 1;
+  usv.subvl = 1;
 #endif
 }