Implement debug havereset bits

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 35adc10f9907eec29754127b3ca1abedb8c2bba3..5a57c285c9bcada230568c2bc76991987c8a9fd3 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -154,6 +154,8 @@ void processor_t::reset()
 
   if (ext)
     ext->reset(); // reset the extension
+
+  sim->proc_reset(id);
 }
 
 // Count number of contiguous 0 bits starting from the LSB.