add subvl to headers, comment out state-cfg

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index a30c2e36d527665393896b4ac31d9dc5f7fa5d89..934a6b0eeadb5ed233e87dcc5db41492d1acd399 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -511,17 +511,17 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       reg_t destoffs = get_field(val, SV_STATE_DESTOFFS);
       state.sv().srcoffs  = std::min(srcoffs , state.sv().vl-1);
       state.sv().destoffs = std::min(destoffs, state.sv().vl-1);
-      int state_bank = get_field(val, SV_STATE_BANK);
-      int state_size = get_field(val, SV_STATE_SIZE);
-      set_csr(CSR_USVCFG, state_bank | (state_size << 3));
+      //int state_bank = get_field(val, SV_STATE_BANK);
+      //int state_size = get_field(val, SV_STATE_SIZE);
+      //set_csr(CSR_USVCFG, state_bank | (state_size << 3));
       break;
     }
     case CSR_USVCFG:
     {
       int old_bank = state.sv().state_bank;
       int old_size = state.sv().state_size;
-      state.sv().state_bank = get_field(val, SV_STATE_BANK);
-      state.sv().state_size = get_field(val, SV_STATE_SIZE);
+      state.sv().state_bank = get_field(val, SV_CFG_BANK);
+      state.sv().state_size = get_field(val, SV_CFG_SIZE) >> 3;
       if (old_bank != state.sv().state_bank ||
           old_size != state.sv().state_size)
       {