Narrow the interface used by the processors and memory to the top-level simulator...

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 943951b322def34cc8bd079d2ec74e704a419b13..ce040443977a61faecf7d243dcbedf685574f71c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -19,7 +19,7 @@
 #undef STATE
 #define STATE state
 
-processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
+processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
         bool halt_on_reset)
   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
   halt_on_reset(halt_on_reset), last_pc(1), executions(1)