add predication remap option

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 773fab85c0d5efde829469657cb998b46c4c143a..f84aa8f91e9c85fec755061b7863594a78f82bda 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -193,13 +193,13 @@ sv_csr_t &state_t::sv()
     return get_usv();
 }
 
-sv_shape_t* state_t::get_shape(reg_t reg)
+sv_shape_t* state_t::get_shape(reg_t reg, bool pred)
 {
     if (prv == PRV_M || prv == PRV_S || reg == 0) {
         return NULL;
     }
     for (int i = 0; i < 3; i++) {
-        if (remap[i].regidx == reg) {
+        if (remap[i].regidx == reg && remap[i].pred == pred) {
             return &shape[i];
         }
     }
@@ -614,6 +614,9 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       state.remap[0].regidx = get_field(val, SV_REMAP_REGIDX0);
       state.remap[1].regidx = get_field(val, SV_REMAP_REGIDX1);
       state.remap[2].regidx = get_field(val, SV_REMAP_REGIDX2);
+      state.remap[0].pred = get_field(val, SV_REMAP_PRED0);
+      state.remap[1].pred = get_field(val, SV_REMAP_PRED1);
+      state.remap[2].pred = get_field(val, SV_REMAP_PRED2);
       state.remap[0].shape = get_field(val, SV_REMAP_SHAPE0);
       state.remap[1].shape = get_field(val, SV_REMAP_SHAPE1);
       state.remap[2].shape = get_field(val, SV_REMAP_SHAPE2);