// advertise support for supervisor and user modes
isa |= 1L << ('s' - 'a');
isa |= 1L << ('u' - 'a');
+
+ max_isa = isa;
}
void state_t::reset()
mtvec = DEFAULT_MTVEC;
load_reservation = -1;
tselect = 0;
- for (unsigned int i = 0; i < num_triggers; i++) {
+ for (unsigned int i = 0; i < num_triggers; i++)
mcontrol[i].type = 2;
- mcontrol[i].action = ACTION_NONE;
- tdata1[i] = 0;
- }
}
void processor_t::set_debug(bool value)
set_privilege(PRV_M);
state.dpc = state.pc;
state.pc = DEBUG_ROM_START;
- //debug = true; // TODO
- update_slow_path();
}
void processor_t::take_trap(trap_t& t, reg_t epc)
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
+ case CSR_MINSTRET:
+ case CSR_MCYCLE:
+ if (xlen == 32)
+ state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
+ else
+ state.minstret = val;
+ break;
+ case CSR_MINSTRETH:
+ case CSR_MCYCLEH:
+ state.minstret = (val << 32) | (state.minstret << 32 >> 32);
+ break;
case CSR_MUCOUNTEREN:
- state.mucounteren = val & 7;
+ state.mucounteren = val;
break;
case CSR_MSCOUNTEREN:
- state.mscounteren = val & 7;
+ state.mscounteren = val;
break;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
- case CSR_TSELECT: state.tselect = val; break;
- case CSR_TDATA0:
- if (state.tselect < state.num_triggers) {
+ case CSR_MISA: {
+ if (!(val & (1L << ('F' - 'A'))))
+ val &= ~(1L << ('D' - 'A'));
+
+ // allow MAFDC bits in MISA to be modified
+ reg_t mask = 0;
+ mask |= 1L << ('M' - 'A');
+ mask |= 1L << ('A' - 'A');
+ mask |= 1L << ('F' - 'A');
+ mask |= 1L << ('D' - 'A');
+ mask |= 1L << ('C' - 'A');
+ mask &= max_isa;
+
+ isa = (val & mask) | (isa & ~mask);
+ break;
+ }
+ case CSR_TSELECT:
+ if (val < state.num_triggers) {
+ state.tselect = val;
+ }
+ break;
+ case CSR_TDATA1:
+ {
mcontrol_t *mc = &state.mcontrol[state.tselect];
+ if (mc->dmode && !state.dcsr.cause) {
+ throw trap_illegal_instruction();
+ }
+ mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
mc->select = get_field(val, MCONTROL_SELECT);
+ mc->timing = get_field(val, MCONTROL_TIMING);
mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
mc->chain = get_field(val, MCONTROL_CHAIN);
mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
mc->store = get_field(val, MCONTROL_STORE);
mc->load = get_field(val, MCONTROL_LOAD);
// Assume we're here because of csrw.
+ if (mc->execute)
+ mc->timing = 0;
+ if (mc->load)
+ mc->timing = 1;
trigger_updated();
}
break;
- case CSR_TDATA1:
+ case CSR_TDATA2:
if (state.tselect < state.num_triggers) {
- state.tdata1[state.tselect] = val;
+ state.tdata2[state.tselect] = val;
}
break;
case CSR_DCSR:
reg_t processor_t::get_csr(int which)
{
+ reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
+ state.prv == PRV_S ? state.mscounteren : -1U;
+ bool ctr_ok = (ctr_en >> (which & 31)) & 1;
+
+ if (ctr_ok) {
+ if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
+ return 0;
+ if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
+ return 0;
+ }
+ if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
+ return 0;
+ if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
+ return 0;
+ if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
+ return 0;
+
switch (which)
{
case CSR_FFLAGS:
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
- case CSR_TIME:
case CSR_INSTRET:
case CSR_CYCLE:
- if ((state.mucounteren >> (which & (xlen-1))) & 1)
- return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+ if (ctr_ok)
+ return state.minstret;
break;
- case CSR_STIME:
- case CSR_SINSTRET:
- case CSR_SCYCLE:
- if ((state.mscounteren >> (which & (xlen-1))) & 1)
- return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+ case CSR_MINSTRET:
+ case CSR_MCYCLE:
+ return state.minstret;
+ case CSR_MINSTRETH:
+ case CSR_MCYCLEH:
+ if (xlen == 32)
+ return state.minstret >> 32;
break;
case CSR_MUCOUNTEREN: return state.mucounteren;
case CSR_MSCOUNTEREN: return state.mscounteren;
- case CSR_MUCYCLE_DELTA: return 0;
- case CSR_MUTIME_DELTA: return 0;
- case CSR_MUINSTRET_DELTA: return 0;
- case CSR_MSCYCLE_DELTA: return 0;
- case CSR_MSTIME_DELTA: return 0;
- case CSR_MSINSTRET_DELTA: return 0;
- case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MCYCLE: return state.minstret;
- case CSR_MINSTRET: return state.minstret;
- case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
- case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
| SSTATUS_XS | SSTATUS_PUM;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
case CSR_TSELECT: return state.tselect;
- case CSR_TDATA0:
+ case CSR_TDATA1:
if (state.tselect < state.num_triggers) {
reg_t v = 0;
mcontrol_t *mc = &state.mcontrol[state.tselect];
- v = set_field(v, 0xfL << (xlen-4), mc->type);
- v = set_field(v, 0x3fL << (xlen-10), mc->maskmax);
+ v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
+ v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
+ v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
v = set_field(v, MCONTROL_SELECT, mc->select);
+ v = set_field(v, MCONTROL_TIMING, mc->timing);
v = set_field(v, MCONTROL_ACTION, mc->action);
v = set_field(v, MCONTROL_CHAIN, mc->chain);
v = set_field(v, MCONTROL_MATCH, mc->match);
return 0;
}
break;
- case CSR_TDATA1:
+ case CSR_TDATA2:
if (state.tselect < state.num_triggers) {
- return state.tdata1[state.tselect];
+ return state.tdata2[state.tselect];
} else {
return 0;
}
break;
+ case CSR_TDATA3: return 0;
case CSR_DCSR:
{
uint32_t v = 0;
v = set_field(v, DCSR_XDEBUGVER, 1);
- v = set_field(v, DCSR_HWBPCOUNT, 0);
v = set_field(v, DCSR_NDRESET, 0);
v = set_field(v, DCSR_FULLRESET, 0);
v = set_field(v, DCSR_PRV, state.dcsr.prv);
mmu->check_triggers_store = false;
for (unsigned i = 0; i < state.num_triggers; i++) {
- if (state.mcontrol[i].action == ACTION_NONE)
- continue;
if (state.mcontrol[i].execute) {
mmu->check_triggers_fetch = true;
}
projects / riscv-isa-sim.git / blobdiff