#include "common.h"
#include "config.h"
#include "sim.h"
+#include "htif.h"
#include "disasm.h"
#include <cinttypes>
#include <cmath>
#include <iostream>
#include <assert.h>
#include <limits.h>
+#include <stdexcept>
+#include <algorithm>
-processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
- : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
+#undef STATE
+#define STATE state
+
+processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
+ : sim(sim), ext(NULL), disassembler(new disassembler_t),
+ id(id), run(false), debug(false)
{
- reset(true);
+ parse_isa_string(isa);
+
+ mmu = new mmu_t(sim->mem, sim->memsz);
mmu->set_processor(this);
- #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
- #include "opcodes.h"
- #undef DECLARE_INSN
+ reset(true);
+
+ register_base_instructions();
}
processor_t::~processor_t()
{
+#ifdef RISCV_ENABLE_HISTOGRAM
+ if (histogram_enabled)
+ {
+ fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
+ for (auto it : pc_histogram)
+ fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
+ }
+#endif
+
+ delete mmu;
+ delete disassembler;
}
-void state_t::reset()
+static void bad_isa_string(const char* isa)
{
- // the ISA guarantees on boot that the PC is 0x2000 and the the processor
- // is in supervisor mode, and in 64-bit mode, if supported, with traps
- // and virtual memory disabled.
- sr = SR_S;
-#ifdef RISCV_ENABLE_64BIT
- sr |= SR_S64;
-#endif
- pc = 0x2000;
-
- // the following state is undefined upon boot-up,
- // but we zero it for determinism
- XPR.reset();
- FPR.reset();
-
- evec = 0;
- epc = 0;
- badvaddr = 0;
- cause = 0;
- pcr_k0 = 0;
- pcr_k1 = 0;
- count = 0;
- compare = 0;
- cycle = 0;
- fsr = 0;
+ fprintf(stderr, "error: bad --isa option %s\n", isa);
+ abort();
+}
+void processor_t::parse_isa_string(const char* str)
+{
+ std::string lowercase, tmp;
+ for (const char *r = str; *r; r++)
+ lowercase += std::tolower(*r);
+
+ const char* p = lowercase.c_str();
+ const char* all_subsets = "imafdc";
+
+ max_xlen = 64;
+ isa = reg_t(2) << 62;
+
+ if (strncmp(p, "rv32", 4) == 0)
+ max_xlen = 32, isa = reg_t(1) << 30, p += 4;
+ else if (strncmp(p, "rv64", 4) == 0)
+ p += 4;
+ else if (strncmp(p, "rv", 2) == 0)
+ p += 2;
+
+ if (!*p) {
+ p = all_subsets;
+ } else if (*p == 'g') { // treat "G" as "IMAFD"
+ tmp = std::string("imafd") + (p+1);
+ p = &tmp[0];
+ } else if (*p != 'i') {
+ bad_isa_string(str);
+ }
+
+ isa_string = "rv" + std::to_string(max_xlen) + p;
+ isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+
+ while (*p) {
+ isa |= 1L << (*p - 'a');
+
+ if (auto next = strchr(all_subsets, *p)) {
+ all_subsets = next + 1;
+ p++;
+ } else if (*p == 'x') {
+ const char* ext = p+1, *end = ext;
+ while (islower(*end))
+ end++;
+ register_extension(find_extension(std::string(ext, end - ext).c_str())());
+ p = end;
+ } else {
+ bad_isa_string(str);
+ }
+ }
+
+ if (supports_extension('D') && !supports_extension('F'))
+ bad_isa_string(str);
+
+ // advertise support for supervisor and user modes
+ isa |= 1L << ('s' - 'a');
+ isa |= 1L << ('u' - 'a');
+}
+
+void state_t::reset()
+{
+ memset(this, 0, sizeof(*this));
+ prv = PRV_M;
+ pc = DEFAULT_RSTVEC;
load_reservation = -1;
}
+void processor_t::set_debug(bool value)
+{
+ debug = value;
+ if (ext)
+ ext->set_debug(value);
+}
+
+void processor_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+#ifndef RISCV_ENABLE_HISTOGRAM
+ if (value) {
+ fprintf(stderr, "PC Histogram support has not been properly enabled;");
+ fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
+ }
+#endif
+}
+
void processor_t::reset(bool value)
{
if (run == !value)
run = !value;
state.reset();
+ set_csr(CSR_MSTATUS, state.mstatus);
+
+ if (ext)
+ ext->reset(); // reset the extension
}
-uint32_t processor_t::set_fsr(uint32_t val)
+void processor_t::raise_interrupt(reg_t which)
{
- uint32_t old_fsr = state.fsr;
- state.fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
- return old_fsr;
+ throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
}
-void processor_t::take_interrupt()
+static int ctz(reg_t val)
{
- uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
- interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
-
- if (interrupts && (state.sr & SR_EI))
- for (int i = 0; ; i++, interrupts >>= 1)
- if (interrupts & 1)
- throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
+ int res = 0;
+ if (val)
+ while ((val & 1) == 0)
+ val >>= 1, res++;
+ return res;
}
-void processor_t::step(size_t n, bool noisy)
+void processor_t::take_interrupt()
{
- if(!run)
- return;
+ check_timer();
- size_t i = 0;
- reg_t npc = state.pc;
- mmu_t* _mmu = mmu;
+ reg_t pending_interrupts = state.mip & state.mie;
- try
- {
- take_interrupt();
-
- // execute_insn fetches and executes one instruction
- #define execute_insn(noisy) \
- do { \
- mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
- if(noisy) disasm(fetch.insn, npc); \
- npc = fetch.func(this, fetch.insn, npc); \
- } while(0)
-
- if(noisy) for( ; i < n; i++) // print out instructions as we go
- execute_insn(true);
- else
- {
- // unrolled for speed
- for( ; n > 3 && i < n-3; i+=4)
- {
- execute_insn(false);
- execute_insn(false);
- execute_insn(false);
- execute_insn(false);
- }
- for( ; i < n; i++)
- execute_insn(false);
- }
+ reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
+ reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
+ reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
- state.pc = npc;
- }
- catch(trap_t& t)
- {
- take_trap(npc, t, noisy);
- }
+ reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
+ reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
+ enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
- state.cycle += i;
+ if (enabled_interrupts)
+ raise_interrupt(ctz(enabled_interrupts));
+}
- // update timer and possibly register a timer interrupt
- uint32_t old_count = state.count;
- state.count += i;
- if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
- set_interrupt(IRQ_TIMER, true);
+void processor_t::check_timer()
+{
+ if (sim->rtc >= state.mtimecmp)
+ state.mip |= MIP_MTIP;
}
-void processor_t::take_trap(reg_t pc, trap_t& t, bool noisy)
+static bool validate_priv(reg_t priv)
{
- if (noisy)
- fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
- id, t.name(), pc);
+ return priv == PRV_U || priv == PRV_S || priv == PRV_M;
+}
+
+void processor_t::set_privilege(reg_t prv)
+{
+ assert(validate_priv(prv));
+ mmu->flush_tlb();
+ state.prv = prv;
+}
- // switch to supervisor, set previous supervisor bit, disable interrupts
- set_pcr(PCR_SR, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
- ((state.sr & SR_S) ? SR_PS : 0) |
- ((state.sr & SR_EI) ? SR_PEI : 0));
+void processor_t::take_trap(trap_t& t, reg_t epc)
+{
+ if (debug)
+ fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
+ id, t.name(), epc);
+
+ // by default, trap to M-mode, unless delegated to S-mode
+ reg_t bit = t.cause();
+ reg_t deleg = state.medeleg;
+ if (bit & ((reg_t)1 << (max_xlen-1)))
+ deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
+ if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
+ // handle the trap in S-mode
+ state.pc = state.stvec;
+ state.scause = t.cause();
+ state.sepc = epc;
+ if (t.has_badaddr())
+ state.sbadaddr = t.get_badaddr();
+
+ reg_t s = state.mstatus;
+ s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
+ s = set_field(s, MSTATUS_SPP, state.prv);
+ s = set_field(s, MSTATUS_SIE, 0);
+ set_csr(CSR_MSTATUS, s);
+ set_privilege(PRV_S);
+ } else {
+ state.pc = DEFAULT_MTVEC;
+ state.mcause = t.cause();
+ state.mepc = epc;
+ if (t.has_badaddr())
+ state.mbadaddr = t.get_badaddr();
+
+ reg_t s = state.mstatus;
+ s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
+ s = set_field(s, MSTATUS_MPP, state.prv);
+ s = set_field(s, MSTATUS_MIE, 0);
+ set_csr(CSR_MSTATUS, s);
+ set_privilege(PRV_M);
+ }
yield_load_reservation();
- state.cause = t.cause();
- state.epc = pc;
- state.pc = state.evec;
-
- t.side_effects(&state); // might set badvaddr etc.
}
-void processor_t::deliver_ipi()
+void processor_t::disasm(insn_t insn)
{
- if (run)
- set_pcr(PCR_CLR_IPI, 1);
+ uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+ id, state.pc, bits, disassembler->disassemble(insn).c_str());
}
-void processor_t::disasm(insn_t insn, reg_t pc)
+static bool validate_vm(int max_xlen, reg_t vm)
{
- // the disassembler is stateless, so we share it
- static disassembler disasm;
- fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
- id, state.pc, insn.bits, disasm.disassemble(insn).c_str());
+ if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
+ return true;
+ if (max_xlen == 32 && vm == VM_SV32)
+ return true;
+ return vm == VM_MBARE;
}
-reg_t processor_t::set_pcr(int which, reg_t val)
+void processor_t::set_csr(int which, reg_t val)
{
- reg_t old_pcr = get_pcr(which);
-
+ val = zext_xlen(val);
+ reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP);
+ reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
switch (which)
{
- case PCR_SR:
- state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
-#ifndef RISCV_ENABLE_64BIT
- state.sr &= ~(SR_S64 | SR_U64);
-#endif
-#ifndef RISCV_ENABLE_FPU
- state.sr &= ~SR_EF;
-#endif
-#ifndef RISCV_ENABLE_VEC
- state.sr &= ~SR_EV;
-#endif
- state.sr &= ~SR_ZERO;
- mmu->flush_tlb();
+ case CSR_FFLAGS:
+ dirty_fp_state;
+ state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
+ break;
+ case CSR_FRM:
+ dirty_fp_state;
+ state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
break;
- case PCR_EPC:
- state.epc = val;
+ case CSR_FCSR:
+ dirty_fp_state;
+ state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
+ state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
- case PCR_EVEC:
- state.evec = val;
+ case CSR_MSTATUS: {
+ if ((val ^ state.mstatus) &
+ (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
+ mmu->flush_tlb();
+
+ reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
+ | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
+ | (ext ? MSTATUS_XS : 0);
+
+ if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
+ mask |= MSTATUS_VM;
+ if (validate_priv(get_field(val, MSTATUS_MPP)))
+ mask |= MSTATUS_MPP;
+
+ state.mstatus = (state.mstatus & ~mask) | (val & mask);
+
+ bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
+ dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
+ if (max_xlen == 32)
+ state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
+ else
+ state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
+
+ // spike supports the notion of xlen < max_xlen, but current priv spec
+ // doesn't provide a mechanism to run RV32 software on an RV64 machine
+ xlen = max_xlen;
break;
- case PCR_COUNT:
- state.count = val;
+ }
+ case CSR_MIP: {
+ reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP;
+ state.mip = (state.mip & ~mask) | (val & mask);
break;
- case PCR_COMPARE:
- set_interrupt(IRQ_TIMER, false);
- state.compare = val;
+ }
+ case CSR_MIPI:
+ state.mip = set_field(state.mip, MIP_MSIP, val & 1);
break;
- case PCR_PTBR:
- state.ptbr = val & ~(PGSIZE-1);
+ case CSR_MIE:
+ state.mie = (state.mie & ~all_ints) | (val & all_ints);
break;
- case PCR_SEND_IPI:
- sim->send_ipi(val);
+ case CSR_MIDELEG:
+ state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
- case PCR_CLR_IPI:
- set_interrupt(IRQ_IPI, val & 1);
+ case CSR_MEDELEG: {
+ reg_t mask = 0;
+#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
+#include "encoding.h"
+#undef DECLARE_CAUSE
+ state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
- case PCR_SUP0:
- state.pcr_k0 = val;
+ }
+ case CSR_MUCOUNTEREN:
+ state.mucounteren = val & 7;
break;
- case PCR_SUP1:
- state.pcr_k1 = val;
+ case CSR_MSCOUNTEREN:
+ state.mscounteren = val & 7;
break;
- case PCR_TOHOST:
+ case CSR_SSTATUS: {
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
+ }
+ case CSR_SIP:
+ return set_csr(CSR_MIP,
+ (state.mip & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SIE:
+ return set_csr(CSR_MIE,
+ (state.mie & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SEPC: state.sepc = val; break;
+ case CSR_STVEC: state.stvec = val >> 2 << 2; break;
+ case CSR_SPTBR: state.sptbr = val; break;
+ case CSR_SSCRATCH: state.sscratch = val; break;
+ case CSR_SCAUSE: state.scause = val; break;
+ case CSR_SBADADDR: state.sbadaddr = val; break;
+ case CSR_MEPC: state.mepc = val; break;
+ case CSR_MSCRATCH: state.mscratch = val; break;
+ case CSR_MCAUSE: state.mcause = val; break;
+ case CSR_MBADADDR: state.mbadaddr = val; break;
+ case CSR_MTIMECMP:
+ state.mip &= ~MIP_MTIP;
+ state.mtimecmp = val;
+ break;
+ case CSR_MTOHOST:
if (state.tohost == 0)
state.tohost = val;
break;
- case PCR_FROMHOST:
- set_interrupt(IRQ_HOST, val != 0);
+ case CSR_MFROMHOST:
+ state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
state.fromhost = val;
break;
}
-
- return old_pcr;
}
-reg_t processor_t::get_pcr(int which)
+reg_t processor_t::get_csr(int which)
{
switch (which)
{
- case PCR_SR:
- return state.sr;
- case PCR_EPC:
- return state.epc;
- case PCR_BADVADDR:
- return state.badvaddr;
- case PCR_EVEC:
- return state.evec;
- case PCR_COUNT:
- return state.count;
- case PCR_COMPARE:
- return state.compare;
- case PCR_CAUSE:
- return state.cause;
- case PCR_PTBR:
- return state.ptbr;
- case PCR_ASID:
- return 0;
- case PCR_FATC:
- mmu->flush_tlb();
- return 0;
- case PCR_HARTID:
- return id;
- case PCR_IMPL:
- return 1;
- case PCR_SUP0:
- return state.pcr_k0;
- case PCR_SUP1:
- return state.pcr_k1;
- case PCR_TOHOST:
+ case CSR_FFLAGS:
+ require_fp;
+ if (!supports_extension('F'))
+ break;
+ return state.fflags;
+ case CSR_FRM:
+ require_fp;
+ if (!supports_extension('F'))
+ break;
+ return state.frm;
+ case CSR_FCSR:
+ require_fp;
+ if (!supports_extension('F'))
+ break;
+ return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
+ case CSR_TIME:
+ case CSR_INSTRET:
+ case CSR_CYCLE:
+ if ((state.mucounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+ break;
+ case CSR_STIME:
+ case CSR_SINSTRET:
+ case CSR_SCYCLE:
+ if ((state.mscounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+ break;
+ case CSR_MUCOUNTEREN: return state.mucounteren;
+ case CSR_MSCOUNTEREN: return state.mscounteren;
+ case CSR_MUCYCLE_DELTA: return 0;
+ case CSR_MUTIME_DELTA: return 0;
+ case CSR_MUINSTRET_DELTA: return 0;
+ case CSR_MSCYCLE_DELTA: return 0;
+ case CSR_MSTIME_DELTA: return 0;
+ case CSR_MSINSTRET_DELTA: return 0;
+ case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MTIME: return sim->rtc;
+ case CSR_MCYCLE: return state.minstret;
+ case CSR_MINSTRET: return state.minstret;
+ case CSR_MTIMEH: if (xlen > 32) break; else return sim->rtc >> 32;
+ case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_SSTATUS: {
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ reg_t sstatus = state.mstatus & mask;
+ if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
+ (sstatus & SSTATUS_XS) == SSTATUS_XS)
+ sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
+ return sstatus;
+ }
+ case CSR_SIP: return state.mip & state.mideleg;
+ case CSR_SIE: return state.mie & state.mideleg;
+ case CSR_SEPC: return state.sepc;
+ case CSR_SBADADDR: return state.sbadaddr;
+ case CSR_STVEC: return state.stvec;
+ case CSR_SCAUSE:
+ if (max_xlen > xlen)
+ return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
+ return state.scause;
+ case CSR_SPTBR: return state.sptbr;
+ case CSR_SASID: return 0;
+ case CSR_SSCRATCH: return state.sscratch;
+ case CSR_MSTATUS: return state.mstatus;
+ case CSR_MIP: return state.mip;
+ case CSR_MIPI: return 0;
+ case CSR_MIE: return state.mie;
+ case CSR_MEPC: return state.mepc;
+ case CSR_MSCRATCH: return state.mscratch;
+ case CSR_MCAUSE: return state.mcause;
+ case CSR_MBADADDR: return state.mbadaddr;
+ case CSR_MTIMECMP: return state.mtimecmp;
+ case CSR_MISA: return isa;
+ case CSR_MARCHID: return 0;
+ case CSR_MIMPID: return 0;
+ case CSR_MVENDORID: return 0;
+ case CSR_MHARTID: return id;
+ case CSR_MTVEC: return DEFAULT_MTVEC;
+ case CSR_MEDELEG: return state.medeleg;
+ case CSR_MIDELEG: return state.mideleg;
+ case CSR_MTOHOST:
+ sim->get_htif()->tick(); // not necessary, but faster
return state.tohost;
- case PCR_FROMHOST:
+ case CSR_MFROMHOST:
+ sim->get_htif()->tick(); // not necessary, but faster
return state.fromhost;
+ case CSR_MCFGADDR: return sim->memsz;
+ case CSR_UARCH0:
+ case CSR_UARCH1:
+ case CSR_UARCH2:
+ case CSR_UARCH3:
+ case CSR_UARCH4:
+ case CSR_UARCH5:
+ case CSR_UARCH6:
+ case CSR_UARCH7:
+ case CSR_UARCH8:
+ case CSR_UARCH9:
+ case CSR_UARCH10:
+ case CSR_UARCH11:
+ case CSR_UARCH12:
+ case CSR_UARCH13:
+ case CSR_UARCH14:
+ case CSR_UARCH15:
+ return 0;
}
- return -1;
-}
-
-void processor_t::set_interrupt(int which, bool on)
-{
- uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
- if (on)
- state.sr |= mask;
- else
- state.sr &= ~mask;
+ throw trap_illegal_instruction();
}
reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
insn_func_t processor_t::decode_insn(insn_t insn)
{
- bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
+ // look up opcode in hash table
+ size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
+ insn_desc_t desc = opcode_cache[idx];
+
+ if (unlikely(insn.bits() != desc.match)) {
+ // fall back to linear search
+ insn_desc_t* p = &instructions[0];
+ while ((insn.bits() & p->mask) != p->match)
+ p++;
+ desc = *p;
+
+ if (p->mask != 0 && p > &instructions[0]) {
+ if (p->match != (p-1)->match && p->match != (p+1)->match) {
+ // move to front of opcode list to reduce miss penalty
+ while (--p >= &instructions[0])
+ *(p+1) = *p;
+ instructions[0] = desc;
+ }
+ }
- auto key = insn.bits & ((1L << opcode_bits)-1);
- for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
- if ((insn.bits & it->second.mask) == it->second.match)
- return rv64 ? it->second.rv64 : it->second.rv32;
+ opcode_cache[idx] = desc;
+ opcode_cache[idx].match = insn.bits();
+ }
- return &illegal_instruction;
+ return xlen == 64 ? desc.rv64 : desc.rv32;
}
void processor_t::register_insn(insn_desc_t desc)
{
- assert(desc.mask & 1);
- if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
- {
- unsigned x = 0;
- while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
- (opcode_bits == 0 || x <= opcode_bits))
- x++;
- opcode_bits = x;
-
- decltype(opcode_map) new_map;
- for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
- new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
- opcode_map = new_map;
- }
+ instructions.push_back(desc);
+}
+
+void processor_t::build_opcode_map()
+{
+ struct cmp {
+ bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
+ if (lhs.match == rhs.match)
+ return lhs.mask > rhs.mask;
+ return lhs.match > rhs.match;
+ }
+ };
+ std::sort(instructions.begin(), instructions.end(), cmp());
- opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
+ for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
+ opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
}
void processor_t::register_extension(extension_t* x)
{
for (auto insn : x->get_instructions())
register_insn(insn);
+ build_opcode_map();
+ for (auto disasm_insn : x->get_disasms())
+ disassembler->add_insn(disasm_insn);
if (ext != NULL)
throw std::logic_error("only one extension may be registered");
ext = x;
x->set_processor(this);
}
+
+void processor_t::register_base_instructions()
+{
+ #define DECLARE_INSN(name, match, mask) \
+ insn_bits_t name##_match = (match), name##_mask = (mask);
+ #include "encoding.h"
+ #undef DECLARE_INSN
+
+ #define DEFINE_INSN(name) \
+ REGISTER_INSN(this, name, name##_match, name##_mask)
+ #include "insn_list.h"
+ #undef DEFINE_INSN
+
+ register_insn({0, 0, &illegal_instruction, &illegal_instruction});
+ build_opcode_map();
+}
+
+bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
+{
+ try {
+ auto res = get_csr(addr / (max_xlen / 8));
+ memcpy(bytes, &res, len);
+ return true;
+ } catch (trap_illegal_instruction& t) {
+ return false;
+ }
+}
+
+bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+ try {
+ reg_t value = 0;
+ memcpy(&value, bytes, len);
+ set_csr(addr / (max_xlen / 8), value);
+ return true;
+ } catch (trap_illegal_instruction& t) {
+ return false;
+ }
+}