Rename tdata[0-2] to tdata[1-3].

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7d8c5df64e9cb6f78d3b57c810983d5c22aec2cd..57823f536a0f4c9d808635c20fa54ba627314fbd 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -119,11 +119,8 @@ void state_t::reset()
   mtvec = DEFAULT_MTVEC;
   load_reservation = -1;
   tselect = 0;
-  for (unsigned int i = 0; i < num_triggers; i++) {
+  for (unsigned int i = 0; i < num_triggers; i++)
     mcontrol[i].type = 2;
-    mcontrol[i].action = ACTION_NONE;
-    tdata1[i] = 0;
-  }
 }
 
 void processor_t::set_debug(bool value)
@@ -384,11 +381,20 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_MSCRATCH: state.mscratch = val; break;
     case CSR_MCAUSE: state.mcause = val; break;
     case CSR_MBADADDR: state.mbadaddr = val; break;
-    case CSR_TSELECT: state.tselect = val; break;
-    case CSR_TDATA0:
-      if (state.tselect < state.num_triggers) {
+    case CSR_TSELECT:
+      if (val < state.num_triggers) {
+        state.tselect = val;
+      }
+      break;
+    case CSR_TDATA1:
+      {
         mcontrol_t *mc = &state.mcontrol[state.tselect];
+        if (mc->dmode && !state.dcsr.cause) {
+          throw trap_illegal_instruction();
+        }
+        mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
         mc->select = get_field(val, MCONTROL_SELECT);
+        mc->timing = get_field(val, MCONTROL_TIMING);
         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
         mc->chain = get_field(val, MCONTROL_CHAIN);
         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
@@ -403,9 +409,9 @@ void processor_t::set_csr(int which, reg_t val)
         trigger_updated();
       }
       break;
-    case CSR_TDATA1:
+    case CSR_TDATA2:
       if (state.tselect < state.num_triggers) {
-        state.tdata1[state.tselect] = val;
+        state.tdata2[state.tselect] = val;
       }
       break;
     case CSR_DCSR:
@@ -512,13 +518,15 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case CSR_TSELECT: return state.tselect;
-    case CSR_TDATA0:
+    case CSR_TDATA1:
       if (state.tselect < state.num_triggers) {
         reg_t v = 0;
         mcontrol_t *mc = &state.mcontrol[state.tselect];
-        v = set_field(v, 0xfL << (xlen-4), mc->type);
-        v = set_field(v, 0x3fL << (xlen-10), mc->maskmax);
+        v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
+        v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
+        v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
         v = set_field(v, MCONTROL_SELECT, mc->select);
+        v = set_field(v, MCONTROL_TIMING, mc->timing);
         v = set_field(v, MCONTROL_ACTION, mc->action);
         v = set_field(v, MCONTROL_CHAIN, mc->chain);
         v = set_field(v, MCONTROL_MATCH, mc->match);
@@ -534,9 +542,9 @@ reg_t processor_t::get_csr(int which)
         return 0;
       }
       break;
-    case CSR_TDATA1:
+    case CSR_TDATA2:
       if (state.tselect < state.num_triggers) {
-        return state.tdata1[state.tselect];
+        return state.tdata2[state.tselect];
       } else {
         return 0;
       }
@@ -679,8 +687,6 @@ void processor_t::trigger_updated()
   mmu->check_triggers_store = false;
 
   for (unsigned i = 0; i < state.num_triggers; i++) {
-    if (state.mcontrol[i].action == ACTION_NONE)
-      continue;
     if (state.mcontrol[i].execute) {
       mmu->check_triggers_fetch = true;
     }