+// See LICENSE for license details.
+
#include "processor.h"
-#include <bfd.h>
-#include <dis-asm.h>
-#include <cmath>
-#include <cstdlib>
-#include <iostream>
#include "common.h"
#include "config.h"
#include "sim.h"
-#include "icsim.h"
+#include "disasm.h"
+#include <cinttypes>
+#include <cmath>
+#include <cstdlib>
+#include <iostream>
+#include <assert.h>
+#include <limits.h>
-processor_t::processor_t(sim_t* _sim, mmu_t* _mmu)
- : sim(_sim), mmu(*_mmu)
+processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
+ : sim(*_sim), mmu(*_mmu), id(_id), opcode_bits(0), utidx(0)
{
- initialize_dispatch_table();
- // a few assumptions about endianness, including freg_t union
- static_assert(BYTE_ORDER == LITTLE_ENDIAN);
- static_assert(sizeof(freg_t) == 8);
- static_assert(sizeof(reg_t) == 8);
-
- static_assert(sizeof(insn_t) == 4);
- static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
+ reset(true);
+ mmu.set_processor(this);
- icsim = NULL;
- dcsim = NULL;
- itlbsim = NULL;
- dtlbsim = NULL;
+ #define DECLARE_INSN(name, match, mask) \
+ register_insn(match, mask, (insn_func_t)&processor_t::rv32_##name, (insn_func_t)&processor_t::rv64_##name);
+ #include "opcodes.h"
+ #undef DECLARE_INSN
- reset();
+ // create microthreads
+ for (int i=0; i<MAX_UTS; i++)
+ uts[i] = new processor_t(&sim, &mmu, id, i);
}
-processor_t::~processor_t()
+processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
+ uint32_t _utidx)
+ : sim(*_sim), mmu(*_mmu), id(_id)
{
- if(icsim)
- icsim->print_stats();
- delete icsim;
-
- if(itlbsim)
- itlbsim->print_stats();
- delete itlbsim;
-
- if(dcsim)
- dcsim->print_stats();
- delete dcsim;
+ reset(true);
+ set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV);
+ utidx = _utidx;
- if(dtlbsim)
- dtlbsim->print_stats();
- delete dtlbsim;
+ // microthreads don't possess their own microthreads
+ for (int i=0; i<MAX_UTS; i++)
+ uts[i] = NULL;
}
-void processor_t::init(uint32_t _id, icsim_t* default_icache,
- icsim_t* default_dcache)
+processor_t::~processor_t()
{
- id = _id;
-
- for (int i=0; i<MAX_UTS; i++)
- {
- uts[i] = new processor_t(sim, &mmu);
- uts[i]->id = id;
- uts[i]->set_sr(uts[i]->sr | SR_EF);
- uts[i]->set_sr(uts[i]->sr | SR_EV);
- uts[i]->utidx = i;
- }
-
- #ifdef RISCV_ENABLE_ICSIM
- icsim = new icsim_t(*default_icache);
- mmu.set_icsim(icsim);
- itlbsim = new icsim_t(1, 8, 4096, "ITLB");
- mmu.set_itlbsim(itlbsim);
- #endif
- #ifdef RISCV_ENABLE_ICSIM
- dcsim = new icsim_t(*default_dcache);
- mmu.set_dcsim(dcsim);
- dtlbsim = new icsim_t(1, 8, 4096, "DTLB");
- mmu.set_dtlbsim(dtlbsim);
- #endif
}
-void processor_t::reset()
+void processor_t::reset(bool value)
{
- run = false;
+ if (run == !value)
+ return;
+ run = !value;
- memset(XPR,0,sizeof(XPR));
- memset(FPR,0,sizeof(FPR));
+ // the ISA guarantees on boot that the PC is 0x2000 and the the processor
+ // is in supervisor mode, and in 64-bit mode, if supported, with traps
+ // and virtual memory disabled.
+ sr = 0;
+ set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM);
+ pc = 0x2000;
+
+ // the following state is undefined upon boot-up,
+ // but we zero it for determinism
+ XPR.reset();
+ FPR.reset();
- pc = 0;
evec = 0;
epc = 0;
badvaddr = 0;
cause = 0;
pcr_k0 = 0;
pcr_k1 = 0;
- tohost = 0;
- fromhost = 0;
count = 0;
compare = 0;
cycle = 0;
- set_sr(SR_S | SR_SX); // SX ignored if 64b mode not supported
set_fsr(0);
// vector stuff
nxfpr_bank = 256;
nxpr_use = 32;
nfpr_use = 32;
- for (int i=0; i<MAX_UTS; i++)
- uts[i] = NULL;
-}
-
-void processor_t::set_sr(uint32_t val)
-{
- sr = val & ~SR_ZERO;
-#ifndef RISCV_ENABLE_64BIT
- sr &= ~(SR_SX | SR_UX);
-#endif
-#ifndef RISCV_ENABLE_FPU
- sr &= ~SR_EF;
-#endif
-#ifndef RISCV_ENABLE_RVC
- sr &= ~SR_EC;
-#endif
-#ifndef RISCV_ENABLE_VEC
- sr &= ~SR_EV;
-#endif
-
- mmu.set_vm_enabled(sr & SR_VM);
- mmu.set_supervisor(sr & SR_S);
- mmu.flush_tlb();
-
- xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
}
void processor_t::set_fsr(uint32_t val)
{
- fsr = val & ~FSR_ZERO;
+ fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
}
void processor_t::vcfg()
void processor_t::take_interrupt()
{
- uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
+ uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT;
interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
if(interrupts && (sr & SR_ET))
- throw trap_interrupt;
+ for(int i = 0; ; i++, interrupts >>= 1)
+ if(interrupts & 1)
+ throw interrupt_t(i);
}
void processor_t::step(size_t n, bool noisy)
return;
size_t i = 0;
- while(1) try
+ try
{
take_interrupt();
- #define execute_insn(noisy) \
- do { insn_t insn = mmu.load_insn(pc, sr & SR_EC); \
- if(noisy) disasm(insn,pc); \
- pc = dispatch_table[insn.bits % DISPATCH_TABLE_SIZE](this, insn, pc); \
- XPR[0] = 0; } while(0)
+ mmu_t& _mmu = mmu;
+ reg_t npc = pc;
- if(noisy) for( ; i < n; i++)
+ // execute_insn fetches and executes one instruction
+ #define execute_insn(noisy) \
+ do { \
+ mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
+ if(noisy) disasm(fetch.insn, npc); \
+ npc = fetch.func(this, fetch.insn, npc); \
+ pc = npc; \
+ } while(0)
+
+ if(noisy) for( ; i < n; i++) // print out instructions as we go
execute_insn(true);
else
{
+ // unrolled for speed
for( ; n > 3 && i < n-3; i+=4)
{
execute_insn(false);
for( ; i < n; i++)
execute_insn(false);
}
-
- break;
}
catch(trap_t t)
{
- i++;
+ // an exception occurred in the target processor
take_trap(t,noisy);
}
- catch(vt_command_t cmd)
+ catch(interrupt_t t)
{
- i++;
- if (cmd == vt_command_stop)
- break;
+ take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy);
}
- catch(halt_t t)
+ catch(vt_command_t cmd)
{
- reset();
- return;
+ // this microthread has finished
+ assert(cmd == vt_command_stop);
}
cycle += i;
- typeof(count) old_count = count;
- typeof(count) max_count = -1;
+ // update timer and possibly register a timer interrupt
+ uint32_t old_count = count;
count += i;
- if(old_count < compare && (count >= compare || old_count > max_count-i))
- cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
+ if(old_count < compare && uint64_t(old_count) + i >= compare)
+ set_interrupt(IRQ_TIMER, true);
}
-void processor_t::take_trap(trap_t t, bool noisy)
+void processor_t::take_trap(reg_t t, bool noisy)
{
- demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
- demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
- id, trap_name(t), (unsigned long long)pc);
if(noisy)
- printf("core %3d: trap %s, pc 0x%016llx\n",
- id, trap_name(t), (unsigned long long)pc);
+ {
+ if ((sreg_t)t < 0)
+ fprintf(stderr, "core %3d: interrupt %d, epc 0x%016" PRIx64 "\n",
+ id, uint8_t(t), pc);
+ else
+ fprintf(stderr, "core %3d: trap %s, epc 0x%016" PRIx64 "\n",
+ id, trap_name(trap_t(t)), pc);
+ }
- set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
- cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT);
+ // switch to supervisor, set previous supervisor bit, disable traps
+ set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
+ cause = t;
epc = pc;
pc = evec;
badvaddr = mmu.get_badvaddr();
void processor_t::deliver_ipi()
{
- cause |= 1 << (IPI_IRQ+CAUSE_IP_SHIFT);
- run = true;
+ if (run)
+ set_pcr(PCR_CLR_IPI, 1);
}
void processor_t::disasm(insn_t insn, reg_t pc)
{
- printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
-
- #ifdef RISCV_HAVE_LIBOPCODES
- disassemble_info info;
- INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
- info.flavour = bfd_target_unknown_flavour;
- info.arch = bfd_arch_mips;
- info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
- info.endian = BFD_ENDIAN_LITTLE;
- info.buffer = (bfd_byte*)&insn;
- info.buffer_length = sizeof(insn);
- info.buffer_vma = pc;
-
- int ret = print_insn_little_mips(pc, &info);
- demand(ret == insn_length(insn.bits), "disasm bug!");
- #else
- printf("unknown");
- #endif
- printf("\n");
+ // the disassembler is stateless, so we share it
+ static disassembler disasm;
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
+ id, pc, insn.bits, disasm.disassemble(insn).c_str());
}
-// if the lower log2(DISPATCH_TABLE_SIZE) bits of an instruction
-// uniquely identify that instruction, the dispatch table points
-// directly to that insn_func. otherwise, we search the short
-// list of instructions that match.
-
-insn_func_t processor_t::dispatch_table[DISPATCH_TABLE_SIZE];
-
-struct insn_chain_t
+void processor_t::set_pcr(int which, reg_t val)
{
- insn_func_t func;
- uint32_t opcode;
- uint32_t mask;
-};
-static std::vector<insn_chain_t> dispatch_chain[DISPATCH_TABLE_SIZE];
+ switch (which)
+ {
+ case PCR_SR:
+ sr = (val & ~SR_IP) | (sr & SR_IP);
+#ifndef RISCV_ENABLE_64BIT
+ sr &= ~(SR_S64 | SR_U64);
+#endif
+#ifndef RISCV_ENABLE_FPU
+ sr &= ~SR_EF;
+#endif
+#ifndef RISCV_ENABLE_RVC
+ sr &= ~SR_EC;
+#endif
+#ifndef RISCV_ENABLE_VEC
+ sr &= ~SR_EV;
+#endif
+ sr &= ~SR_ZERO;
+ mmu.flush_tlb();
+ break;
+ case PCR_EPC:
+ epc = val;
+ break;
+ case PCR_EVEC:
+ evec = val;
+ break;
+ case PCR_COUNT:
+ count = val;
+ break;
+ case PCR_COMPARE:
+ set_interrupt(IRQ_TIMER, false);
+ compare = val;
+ break;
+ case PCR_PTBR:
+ mmu.set_ptbr(val);
+ break;
+ case PCR_SEND_IPI:
+ sim.send_ipi(val);
+ break;
+ case PCR_CLR_IPI:
+ set_interrupt(IRQ_IPI, val & 1);
+ break;
+ case PCR_K0:
+ pcr_k0 = val;
+ break;
+ case PCR_K1:
+ pcr_k1 = val;
+ break;
+ case PCR_VECBANK:
+ vecbanks = val & 0xff;
+ vecbanks_count = __builtin_popcountll(vecbanks);
+ break;
+ case PCR_TOHOST:
+ if (tohost == 0)
+ tohost = val;
+ break;
+ case PCR_FROMHOST:
+ set_interrupt(IRQ_HOST, val != 0);
+ fromhost = val;
+ break;
+ }
+}
-reg_t processor_t::dispatch(insn_t insn, reg_t pc)
+reg_t processor_t::get_pcr(int which)
{
- size_t idx = insn.bits % DISPATCH_TABLE_SIZE;
- for(size_t i = 0; i < dispatch_chain[idx].size(); i++)
+ switch (which)
{
- insn_chain_t& c = dispatch_chain[idx][i];
- if((insn.bits & c.mask) == c.opcode)
- return c.func(this, insn, pc);
+ case PCR_SR:
+ return sr;
+ case PCR_EPC:
+ return epc;
+ case PCR_BADVADDR:
+ return badvaddr;
+ case PCR_EVEC:
+ return evec;
+ case PCR_COUNT:
+ return count;
+ case PCR_COMPARE:
+ return compare;
+ case PCR_CAUSE:
+ return cause;
+ case PCR_PTBR:
+ return mmu.get_ptbr();
+ case PCR_COREID:
+ return id;
+ case PCR_IMPL:
+ return 1;
+ case PCR_K0:
+ return pcr_k0;
+ case PCR_K1:
+ return pcr_k1;
+ case PCR_VECBANK:
+ return vecbanks;
+ case PCR_VECCFG:
+ return nfpr_use << 18 | nxpr_use << 12 | vl;
+ case PCR_TOHOST:
+ return tohost;
+ case PCR_FROMHOST:
+ return fromhost;
}
- throw trap_illegal_instruction;
+ return -1;
}
-void processor_t::initialize_dispatch_table()
+void processor_t::set_interrupt(int which, bool on)
{
- if(dispatch_table[0] != NULL)
- return;
+ uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
+ if (on)
+ sr |= mask;
+ else
+ sr &= ~mask;
+}
- for(size_t i = 0; i < DISPATCH_TABLE_SIZE; i++)
- {
- #define DECLARE_INSN(name, opcode, mask) \
- if((i & (mask)) == ((opcode) & (mask) & (DISPATCH_TABLE_SIZE-1))) \
- dispatch_chain[i].push_back( \
- (insn_chain_t){&processor_t::insn_func_ ## name, opcode, mask});
- #include "opcodes.h"
- #undef DECLARE_INSN
- }
+insn_func_t processor_t::decode_insn(insn_t insn)
+{
+ bool rv64 = (sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64);
+
+ auto key = insn.bits & ((1L << opcode_bits)-1);
+ auto it = opcode_map.find(key);
+ for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
+ if ((insn.bits & it->second.mask) == it->second.match)
+ return rv64 ? it->second.rv64 : it->second.rv32;
+
+ return &processor_t::illegal_instruction;
+}
- for(size_t i = 0; i < DISPATCH_TABLE_SIZE; i++)
+reg_t processor_t::illegal_instruction(insn_t insn, reg_t pc)
+{
+ throw trap_illegal_instruction;
+}
+
+void processor_t::register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64)
+{
+ assert(mask & 1);
+ if (opcode_bits == 0 || (mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
{
- if(dispatch_chain[i].size() == 1)
- dispatch_table[i] = dispatch_chain[i][0].func;
- else
- dispatch_table[i] = &processor_t::dispatch;
+ unsigned x = 0;
+ while ((mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
+ (opcode_bits == 0 || x <= opcode_bits))
+ x++;
+ opcode_bits = x;
+
+ decltype(opcode_map) new_map;
+ for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
+ new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
+ opcode_map = new_map;
}
+
+ opcode_map.insert(std::make_pair(match & ((1L<<opcode_bits)-1),
+ (opcode_map_entry_t){match, mask, rv32, rv64}));
}
projects / riscv-isa-sim.git / blobdiff