Allow delegation of device interrupts

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8714b9765c8689044db1326c6efb9d2693959733..63339b153935d902371cdf86fb33d2c45d6c2e95 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -254,7 +254,7 @@ static bool validate_vm(int max_xlen, reg_t vm)
 void processor_t::set_csr(int which, reg_t val)
 {
   val = zext_xlen(val);
-  reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_COP);
+  reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
   switch (which)
   {
@@ -523,23 +523,20 @@ void processor_t::register_base_instructions()
 
 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 {
-  try {
-    auto res = get_csr(addr / (max_xlen / 8));
-    memcpy(bytes, &res, len);
-    return true;
-  } catch (trap_illegal_instruction& t) {
-    return false;
-  }
+  return false;
 }
 
 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 {
-  try {
-    reg_t value = 0;
-    memcpy(&value, bytes, len);
-    set_csr(addr / (max_xlen / 8), value);
-    return true;
-  } catch (trap_illegal_instruction& t) {
-    return false;
+  switch (addr)
+  {
+    case 0:
+      state.mip &= ~MIP_MSIP;
+      if (bytes[0] & 1)
+        state.mip |= MIP_MSIP;
+      return true;
+
+    default:
+      return false;
   }
 }