register_base_instructions();
mmu = new mmu_t(sim, this);
+
disassembler = new disassembler_t(max_xlen);
+ if (ext)
+ for (auto disasm_insn : ext->get_disasms())
+ disassembler->add_insn(disasm_insn);
reset();
}
misa = max_isa;
prv = PRV_M;
pc = DEFAULT_RSTVEC;
- load_reservation = -1;
tselect = 0;
for (unsigned int i = 0; i < num_triggers; i++)
mcontrol[i].type = 2;
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_M);
}
-
- yield_load_reservation();
}
void processor_t::disasm(insn_t insn)
state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
else
state.minstret = val;
+ // The ISA mandates that if an instruction writes instret, the write
+ // takes precedence over the increment to instret. However, Spike
+ // unconditionally increments instret after executing an instruction.
+ // Correct for this artifact by decrementing instret here.
+ state.minstret--;
break;
case CSR_MINSTRETH:
case CSR_MCYCLEH:
state.minstret = (val << 32) | (state.minstret << 32 >> 32);
+ state.minstret--; // See comment above.
break;
case CSR_SCOUNTEREN:
state.scounteren = val;
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)