Set U bit in misa register

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 50906f64c6e54ae0f8d4f7a063aee55b841fb263..8c267f4964456e64ad5e4a9b944a8f81219e2aa7 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -84,6 +84,7 @@ void processor_t::parse_isa_string(const char* str)
 
   isa_string = "rv" + std::to_string(max_xlen) + p;
   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+  isa |= 1L << ('u' - 'a'); // advertise support for user mode
 
   while (*p) {
     isa |= 1L << (*p - 'a');
@@ -565,7 +566,7 @@ void processor_t::build_opcode_map()
   std::sort(instructions.begin(), instructions.end(), cmp());
 
   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
-    opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
+    opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 }
 
 void processor_t::register_extension(extension_t* x)