#include "sim.h"
#include "htif.h"
#include "disasm.h"
-#include "icache.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#include <stdexcept>
#include <algorithm>
+#undef STATE
+#define STATE state
+
processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
: sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
- id(_id), run(false), debug(false)
+ id(_id), run(false), debug(false), serialized(false)
{
reset(true);
mmu->set_processor(this);
processor_t::~processor_t()
{
+#ifdef RISCV_ENABLE_HISTOGRAM
+ if (histogram_enabled)
+ {
+ fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
+ for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
+ fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
+ }
+ }
+#endif
+
+ delete disassembler;
}
void state_t::reset()
{
- // the ISA guarantees on boot that the PC is 0x2000 and the the processor
- // is in supervisor mode, and in 64-bit mode, if supported, with traps
- // and virtual memory disabled.
- sr = SR_S | SR_S64;
- pc = 0x2000;
-
- // the following state is undefined upon boot-up,
- // but we zero it for determinism
- XPR.reset();
- FPR.reset();
-
- epc = 0;
- badvaddr = 0;
- evec = 0;
- ptbr = 0;
- pcr_k0 = 0;
- pcr_k1 = 0;
- cause = 0;
- tohost = 0;
- fromhost = 0;
- count = 0;
- compare = 0;
- fflags = 0;
- frm = 0;
-
+ memset(this, 0, sizeof(*this));
+ mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
+ mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
+ mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
+#ifdef RISCV_ENABLE_64BIT
+ mstatus = set_field(mstatus, MSTATUS64_UA, UA_RV64);
+ mstatus = set_field(mstatus, MSTATUS64_SA, UA_RV64);
+#endif
+ pc = 0x100;
load_reservation = -1;
}
ext->set_debug(value);
}
+void processor_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+}
+
void processor_t::reset(bool value)
{
if (run == !value)
run = !value;
state.reset(); // reset the core
- set_pcr(CSR_STATUS, state.sr);
+ set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
ext->reset(); // reset the extension
}
+struct serialize_t {};
+
+void processor_t::serialize()
+{
+ if (serialized)
+ serialized = false;
+ else
+ serialized = true, throw serialize_t();
+}
+
+void processor_t::raise_interrupt(reg_t which)
+{
+ throw trap_t(((reg_t)1 << 63) | which);
+}
+
void processor_t::take_interrupt()
{
- uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
- interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
+ int priv = get_field(state.mstatus, MSTATUS_PRV);
+ int ie = get_field(state.mstatus, MSTATUS_IE);
+
+ if (priv < PRV_M || (priv == PRV_M && ie)) {
+ if (get_field(state.mstatus, MSTATUS_MSIP))
+ raise_interrupt(IRQ_IPI);
+
+ if (state.fromhost != 0)
+ raise_interrupt(IRQ_HOST);
+ }
+
+ if (priv < PRV_S || (priv == PRV_S && ie)) {
+ if (get_field(state.mstatus, MSTATUS_SSIP))
+ raise_interrupt(IRQ_IPI);
- if (interrupts && (state.sr & SR_EI))
- for (int i = 0; ; i++, interrupts >>= 1)
- if (interrupts & 1)
- throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
+ if (state.stip && get_field(state.mstatus, MSTATUS_STIE))
+ raise_interrupt(IRQ_TIMER);
+ }
}
-void processor_t::step(size_t n)
+static void commit_log(state_t* state, reg_t pc, insn_t insn)
{
- if(!run)
- return;
+#ifdef RISCV_ENABLE_COMMITLOG
+ if (get_field(state->mstatus, MSTATUS_IE)) {
+ uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
+ if (state->log_reg_write.addr) {
+ fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
+ pc,
+ insn.bits() & mask,
+ state->log_reg_write.addr & 1 ? 'f' : 'x',
+ state->log_reg_write.addr >> 1,
+ state->log_reg_write.data);
+ } else {
+ fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
+ }
+ }
+ state->log_reg_write.addr = 0;
+#endif
+}
+
+inline void processor_t::update_histogram(size_t pc)
+{
+#ifdef RISCV_ENABLE_HISTOGRAM
+ size_t idx = pc >> 2;
+ pc_histogram[idx]++;
+#endif
+}
+
+static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
+{
+ reg_t npc = fetch.func(p, fetch.insn, pc);
+ commit_log(p->get_state(), pc, fetch.insn);
+ p->update_histogram(pc);
+ return npc;
+}
+
+static void update_timer(state_t* state, size_t instret)
+{
+ uint64_t count0 = (uint64_t)(uint32_t)state->scount;
+ state->scount += instret;
+ uint64_t before = count0 - state->stimecmp;
+ if (int64_t(before ^ (before + instret)) < 0)
+ state->stip = true;
+}
+
+static size_t next_timer(state_t* state)
+{
+ return state->stimecmp - (uint32_t)state->scount;
+}
+void processor_t::step(size_t n)
+{
+ size_t instret = 0;
+ reg_t pc = state.pc;
mmu_t* _mmu = mmu;
- auto count32 = decltype(state.compare)(state.count);
- bool count_le_compare = count32 <= state.compare;
- n = std::min(n, size_t(state.compare - count32) | 1);
+
+ if (unlikely(!run || !n))
+ return;
+ n = std::min(n, next_timer(&state) | 1U);
try
{
take_interrupt();
- // execute_insn fetches and executes one instruction
- #define execute_insn(noisy) \
- do { \
- insn_fetch_t fetch = mmu->load_insn(state.pc); \
- if(noisy) disasm(fetch.insn.insn); \
- state.pc = fetch.func(this, fetch.insn.insn, state.pc); \
- } while(0)
-
-
- // special execute_insn for commit log dumping
-#ifdef RISCV_ENABLE_COMMITLOG
- //static disassembler disasmblr;
- #undef execute_insn
- #define execute_insn(noisy) \
- do { \
- insn_fetch_t fetch = _mmu->load_insn(state.pc); \
- if(noisy) disasm(fetch.insn.insn); \
- bool in_spvr = state.sr & SR_S; \
- if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state.pc, fetch.insn.insn.bits()); \
- /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s ", state.pc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
- state.pc = fetch.func(this, fetch.insn.insn, state.pc); \
- } while(0)
-#endif
-
- if (debug) // print out instructions as we go
+ if (unlikely(debug))
{
- for (size_t i = 0; i < n; state.count++, i++)
- execute_insn(true);
+ while (instret++ < n)
+ {
+ insn_fetch_t fetch = mmu->load_insn(pc);
+ disasm(fetch.insn);
+ pc = execute_insn(this, pc, fetch);
+ }
}
- else while (n > 0)
+ else while (instret < n)
{
- size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
- auto ic_entry_init = &_mmu->icache[idx], ic_entry = ic_entry_init;
-
- #define update_count() { \
- size_t i = ic_entry - ic_entry_init; \
- state.count += i; \
- if (i >= n) break; \
- n -= i; }
+ size_t idx = _mmu->icache_index(pc);
+ auto ic_entry = _mmu->access_icache(pc);
#define ICACHE_ACCESS(idx) { \
- insn_t insn = ic_entry->data.insn.insn; \
- insn_func_t func = ic_entry->data.func; \
- if (unlikely(ic_entry->tag != state.pc)) break; \
+ insn_fetch_t fetch = ic_entry->data; \
ic_entry++; \
- state.pc = func(this, insn, state.pc); }
-
- switch (idx) while (true)
- {
- ICACHE_SWITCH;
- update_count();
- ic_entry_init = ic_entry = &_mmu->icache[0];
+ pc = execute_insn(this, pc, fetch); \
+ instret++; \
+ if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
+ if (unlikely(ic_entry->tag != pc)) break; \
}
- _mmu->access_icache(state.pc);
- update_count();
+ switch (idx) {
+ #include "icache.h"
+ }
}
}
catch(trap_t& t)
{
- take_trap(t);
+ pc = take_trap(t, pc);
}
+ catch(serialize_t& s) {}
+
+ state.pc = pc;
+ update_timer(&state, instret);
+}
+
+void processor_t::push_privilege_stack()
+{
+ reg_t s = state.mstatus;
+ s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
+ s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
+ s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
+ s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
+ s = set_field(s, MSTATUS_PRV, PRV_M);
+ s = set_field(s, MSTATUS_MPRV, PRV_M);
+ s = set_field(s, MSTATUS_IE, 0);
+ set_csr(CSR_MSTATUS, s);
+}
- bool count_ge_compare =
- uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
- if (count_le_compare && count_ge_compare)
- set_interrupt(IRQ_TIMER, true);
+void processor_t::pop_privilege_stack()
+{
+ reg_t s = state.mstatus;
+ s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
+ s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
+ s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
+ s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
+ s = set_field(s, MSTATUS_PRV2, PRV_U);
+ s = set_field(s, MSTATUS_IE2, 1);
+ set_csr(CSR_MSTATUS, s);
}
-void processor_t::take_trap(trap_t& t)
+reg_t processor_t::take_trap(trap_t& t, reg_t epc)
{
if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
- id, t.name(), state.pc);
-
- // switch to supervisor, set previous supervisor bit, disable interrupts
- set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
- ((state.sr & SR_S) ? SR_PS : 0) |
- ((state.sr & SR_EI) ? SR_PEI : 0));
+ id, t.name(), epc);
+ reg_t tvec = 0x40 * get_field(state.mstatus, MSTATUS_PRV);
+ push_privilege_stack();
yield_load_reservation();
- state.cause = t.cause();
- state.epc = state.pc;
- state.pc = state.evec;
-
+ state.mcause = t.cause();
+ state.mepc = epc;
t.side_effects(&state); // might set badvaddr etc.
+ return tvec;
}
void processor_t::deliver_ipi()
{
- if (run)
- set_pcr(CSR_CLEAR_IPI, 1);
+ state.mstatus |= MSTATUS_MSIP;
}
void processor_t::disasm(insn_t insn)
{
- // the disassembler is stateless, so we share it
- fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
- id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
+ uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+ id, state.pc, bits, disassembler->disassemble(insn).c_str());
+}
+
+static bool validate_priv(reg_t priv)
+{
+ return priv == PRV_U || priv == PRV_S || priv == PRV_M;
+}
+
+static bool validate_arch(reg_t arch)
+{
+#ifdef RISCV_ENABLE_64BIT
+ if (arch == UA_RV64) return true;
+#endif
+ return arch == UA_RV32;
}
-reg_t processor_t::set_pcr(int which, reg_t val)
+static bool validate_vm(reg_t vm)
{
- reg_t old_pcr = get_pcr(which);
+ // TODO: VM_SV32 support
+#ifdef RISCV_ENABLE_64BIT
+ if (vm == VM_SV43) return true;
+#endif
+ return vm == VM_MBARE;
+}
+void processor_t::set_csr(int which, reg_t val)
+{
switch (which)
{
case CSR_FFLAGS:
+ dirty_fp_state;
state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
break;
case CSR_FRM:
+ dirty_fp_state;
state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
break;
case CSR_FCSR:
+ dirty_fp_state;
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
- case CSR_STATUS:
- state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
-#ifndef RISCV_ENABLE_64BIT
- state.sr &= ~(SR_S64 | SR_U64);
+ case CSR_SCYCLE:
+ case CSR_STIME:
+ case CSR_SINSTRET:
+ state.scount = val; break;
+ case CSR_SCYCLEH:
+ case CSR_STIMEH:
+ case CSR_SINSTRETH:
+ state.scount = (val << 32) | (uint32_t)state.scount;
+ break;
+ case CSR_MSTATUS:
+ {
+ if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_MPRV))
+ mmu->flush_tlb();
+
+ reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1
+ | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE;
+#ifdef RISCV_ENABLE_FPU
+ mask |= MSTATUS_FS;
#endif
-#ifndef RISCV_ENABLE_FPU
- state.sr &= ~SR_EF;
+ if (ext)
+ mask |= MSTATUS_XS;
+ state.mstatus = (state.mstatus & ~mask) | (val & mask);
+
+ if (validate_vm(get_field(val, MSTATUS_VM)))
+ state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM);
+ if (validate_priv(get_field(val, MSTATUS_MPRV)))
+ state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV);
+ if (validate_priv(get_field(val, MSTATUS_PRV)))
+ state.mstatus = (state.mstatus & ~MSTATUS_PRV) | (val & MSTATUS_PRV);
+ if (validate_priv(get_field(val, MSTATUS_PRV1)))
+ state.mstatus = (state.mstatus & ~MSTATUS_PRV1) | (val & MSTATUS_PRV1);
+ if (validate_priv(get_field(val, MSTATUS_PRV2)))
+ state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2);
+ if (validate_priv(get_field(val, MSTATUS_PRV3)))
+ state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3);
+ xlen = 32;
+
+ bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
+ dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
+#ifndef RISCV_ENABLE_64BIT
+ state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
+#else
+ state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
+
+ if (validate_arch(get_field(val, MSTATUS64_UA)))
+ state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
+ if (validate_arch(get_field(val, MSTATUS64_SA)))
+ state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
+ switch (get_field(state.mstatus, MSTATUS_PRV)) {
+ case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
+ case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
+ case PRV_M: xlen = 64; break;
+ default: abort();
+ }
#endif
- if (!ext)
- state.sr &= ~SR_EA;
- state.sr &= ~SR_ZERO;
- rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
- mmu->flush_tlb();
- break;
- case CSR_EPC:
- state.epc = val;
- break;
- case CSR_EVEC:
- state.evec = val;
break;
- case CSR_CYCLE:
- case CSR_TIME:
- case CSR_INSTRET:
- case CSR_COUNT:
- state.count = val;
- break;
- case CSR_COMPARE:
- set_interrupt(IRQ_TIMER, false);
- state.compare = val;
- break;
- case CSR_PTBR:
- state.ptbr = val & ~(PGSIZE-1);
- break;
- case CSR_SEND_IPI:
- sim->send_ipi(val);
- break;
- case CSR_CLEAR_IPI:
- set_interrupt(IRQ_IPI, val & 1);
- break;
- case CSR_SUP0:
- state.pcr_k0 = val;
- break;
- case CSR_SUP1:
- state.pcr_k1 = val;
+ }
+ case CSR_SSTATUS:
+ {
+ reg_t ms = state.mstatus;
+ ms = set_field(ms, MSTATUS_SSIP, get_field(val, SSTATUS_SIP));
+ ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
+ ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
+ ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
+ ms = set_field(ms, MSTATUS64_UA, get_field(val, SSTATUS_UA));
+ ms = set_field(ms, MSTATUS_STIE, get_field(val, SSTATUS_TIE));
+ ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
+ ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
+ return set_csr(CSR_MSTATUS, ms);
+ }
+ case CSR_SEPC: state.sepc = val; break;
+ case CSR_STVEC: state.stvec = val & ~3; break;
+ case CSR_STIMECMP:
+ serialize();
+ state.stip = false;
+ state.stimecmp = val;
break;
+ case CSR_SPTBR: state.sptbr = val & ~(PGSIZE-1); break;
+ case CSR_SSCRATCH: state.sscratch = val; break;
+ case CSR_MEPC: state.mepc = val; break;
+ case CSR_MSCRATCH: state.mscratch = val; break;
+ case CSR_MCAUSE: state.mcause = val; break;
+ case CSR_MBADADDR: state.mbadaddr = val; break;
+ case CSR_SEND_IPI: sim->send_ipi(val); break;
case CSR_TOHOST:
if (state.tohost == 0)
state.tohost = val;
break;
- case CSR_FROMHOST:
- set_fromhost(val);
- break;
+ case CSR_FROMHOST: state.fromhost = val; break;
}
-
- return old_pcr;
-}
-
-void processor_t::set_fromhost(reg_t val)
-{
- set_interrupt(IRQ_HOST, val != 0);
- state.fromhost = val;
}
-reg_t processor_t::get_pcr(int which)
+reg_t processor_t::get_csr(int which)
{
switch (which)
{
case CSR_FFLAGS:
+ require_fp;
return state.fflags;
case CSR_FRM:
+ require_fp;
return state.frm;
case CSR_FCSR:
+ require_fp;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
- case CSR_STATUS:
- return state.sr;
- case CSR_EPC:
- return state.epc;
- case CSR_BADVADDR:
- return state.badvaddr;
- case CSR_EVEC:
- return state.evec;
case CSR_CYCLE:
case CSR_TIME:
case CSR_INSTRET:
- case CSR_COUNT:
- return state.count;
- case CSR_COMPARE:
- return state.compare;
- case CSR_CAUSE:
- return state.cause;
- case CSR_PTBR:
- return state.ptbr;
- case CSR_ASID:
- return 0;
- case CSR_FATC:
- mmu->flush_tlb();
- return 0;
- case CSR_HARTID:
- return id;
- case CSR_IMPL:
- return 1;
- case CSR_SUP0:
- return state.pcr_k0;
- case CSR_SUP1:
- return state.pcr_k1;
+ case CSR_SCYCLE:
+ case CSR_STIME:
+ case CSR_SINSTRET:
+ serialize();
+ return state.scount;
+ case CSR_CYCLEH:
+ case CSR_TIMEH:
+ case CSR_INSTRETH:
+ case CSR_SCYCLEH:
+ case CSR_STIMEH:
+ case CSR_SINSTRETH:
+ if (xlen == 64)
+ break;
+ serialize();
+ return state.scount >> 32;
+ case CSR_SSTATUS:
+ {
+ reg_t ss = 0;
+ ss = set_field(ss, SSTATUS_SIP, get_field(state.mstatus, MSTATUS_SSIP));
+ ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
+ ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
+ ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
+ ss = set_field(ss, SSTATUS_UA, get_field(state.mstatus, MSTATUS64_UA));
+ ss = set_field(ss, SSTATUS_TIE, get_field(state.mstatus, MSTATUS_STIE));
+ ss = set_field(ss, SSTATUS_TIP, state.stip);
+ ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
+ ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
+ if (get_field(state.mstatus, MSTATUS64_SD))
+ ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
+ return ss;
+ }
+ case CSR_SEPC: return state.sepc;
+ case CSR_SBADADDR: return state.sbadaddr;
+ case CSR_STVEC: return state.stvec;
+ case CSR_STIMECMP: return state.stimecmp;
+ case CSR_SCAUSE:
+ if (xlen == 32 && (state.scause >> 63) != 0)
+ return state.scause | ((reg_t)1 << 31);
+ return state.scause;
+ case CSR_SPTBR: return state.sptbr;
+ case CSR_SASID: return 0;
+ case CSR_SSCRATCH: return state.sscratch;
+ case CSR_MSTATUS: return state.mstatus;
+ case CSR_MEPC: return state.mepc;
+ case CSR_MSCRATCH: return state.mscratch;
+ case CSR_MCAUSE: return state.mcause;
+ case CSR_MBADADDR: return state.mbadaddr;
case CSR_TOHOST:
sim->get_htif()->tick(); // not necessary, but faster
return state.tohost;
case CSR_FROMHOST:
sim->get_htif()->tick(); // not necessary, but faster
return state.fromhost;
- default:
- return -1;
+ case CSR_SEND_IPI: return 0;
+ case CSR_HARTID: return id;
+ case CSR_UARCH0:
+ case CSR_UARCH1:
+ case CSR_UARCH2:
+ case CSR_UARCH3:
+ case CSR_UARCH4:
+ case CSR_UARCH5:
+ case CSR_UARCH6:
+ case CSR_UARCH7:
+ case CSR_UARCH8:
+ case CSR_UARCH9:
+ case CSR_UARCH10:
+ case CSR_UARCH11:
+ case CSR_UARCH12:
+ case CSR_UARCH13:
+ case CSR_UARCH14:
+ case CSR_UARCH15:
+ return 0;
}
-}
-
-void processor_t::set_interrupt(int which, bool on)
-{
- uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
- if (on)
- state.sr |= mask;
- else
- state.sr &= ~mask;
+ throw trap_illegal_instruction();
}
reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
while ((insn.bits() & desc->mask) != desc->match)
desc++;
- return rv64 ? desc->rv64 : desc->rv32;
+ return xlen == 64 ? desc->rv64 : desc->rv32;
}
void processor_t::register_insn(insn_desc_t desc)
projects / riscv-isa-sim.git / blobdiff