Remove SCRs; add padding after config string

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ed7c02ffc710b1e4b3c5643081180f440b11ca0e..ccbbd1632102a42b42c594a7e692fcc407642ffb 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -5,6 +5,7 @@
 #include "common.h"
 #include "config.h"
 #include "sim.h"
+#include "mmu.h"
 #include "htif.h"
 #include "disasm.h"
 #include <cinttypes>
@@ -25,8 +26,7 @@ processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
 {
   parse_isa_string(isa);
 
-  mmu = new mmu_t(sim->mem, sim->memsz);
-  mmu->set_processor(this);
+  mmu = new mmu_t(sim, this);
 
   reset(true);
 
@@ -67,7 +67,7 @@ void processor_t::parse_isa_string(const char* str)
   isa = reg_t(2) << 62;
 
   if (strncmp(p, "rv32", 4) == 0)
-    max_xlen = 32, isa = 0, p += 4;
+    max_xlen = 32, isa = reg_t(1) << 30, p += 4;
   else if (strncmp(p, "rv64", 4) == 0)
     p += 4;
   else if (strncmp(p, "rv", 2) == 0)
@@ -105,11 +105,6 @@ void processor_t::parse_isa_string(const char* str)
   if (supports_extension('D') && !supports_extension('F'))
     bad_isa_string(str);
 
-  // if we have IMAFD, advertise G, too
-  if (supports_extension('I') && supports_extension('M') &&
-      supports_extension('A') && supports_extension('D'))
-    isa |= 1L << ('g' - 'a');
-
   // advertise support for supervisor and user modes
   isa |= 1L << ('s' - 'a');
   isa |= 1L << ('u' - 'a');
@@ -170,25 +165,18 @@ static int ctz(reg_t val)
 
 void processor_t::take_interrupt()
 {
-  check_timer();
-
-  reg_t interrupts = state.mip & state.mie;
+  reg_t pending_interrupts = state.mip & state.mie;
 
-  reg_t m_interrupts = interrupts & ~state.mideleg;
   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
-  if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
-    raise_interrupt(ctz(m_interrupts));
+  reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
+  reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 
-  reg_t s_interrupts = interrupts & state.mideleg;
   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
-  if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
-    raise_interrupt(ctz(s_interrupts));
-}
+  reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
+  enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 
-void processor_t::check_timer()
-{
-  if (sim->rtc >= state.mtimecmp)
-    state.mip |= MIP_MTIP;
+  if (enabled_interrupts)
+    raise_interrupt(ctz(enabled_interrupts));
 }
 
 static bool validate_priv(reg_t priv)
@@ -229,7 +217,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     set_csr(CSR_MSTATUS, s);
     set_privilege(PRV_S);
   } else {
-    state.pc = DEFAULT_MTVEC;
+    state.pc = state.mtvec;
     state.mcause = t.cause();
     state.mepc = epc;
     if (t.has_badaddr())
@@ -265,8 +253,8 @@ static bool validate_vm(int max_xlen, reg_t vm)
 void processor_t::set_csr(int which, reg_t val)
 {
   val = zext_xlen(val);
-  reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
-  reg_t s_ints = MIP_SSIP | MIP_STIP;
+  reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP);
+  reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
   switch (which)
   {
     case CSR_FFLAGS:
@@ -311,7 +299,7 @@ void processor_t::set_csr(int which, reg_t val)
       break;
     }
     case CSR_MIP: {
-      reg_t mask = all_ints &~ MIP_MTIP;
+      reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP;
       state.mip = (state.mip & ~mask) | (val & mask);
       break;
     }
@@ -322,7 +310,7 @@ void processor_t::set_csr(int which, reg_t val)
       state.mie = (state.mie & ~all_ints) | (val & all_ints);
       break;
     case CSR_MIDELEG:
-      state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
+      state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
       break;
     case CSR_MEDELEG: {
       reg_t mask = 0;
@@ -341,19 +329,14 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_SSTATUS: {
       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
                  | SSTATUS_XS | SSTATUS_PUM;
-      set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
-      break;
-    }
-    case CSR_SIP: {
-      reg_t mask = s_ints &~ MIP_STIP;
-      state.mip = (state.mip & ~mask) | (val & mask);
-      break;
-    }
-    case CSR_SIE: {
-      reg_t mask = s_ints;
-      state.mie = (state.mie & ~mask) | (val & mask);
-      break;
+      return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
+    case CSR_SIP:
+      return set_csr(CSR_MIP,
+                     (state.mip & ~state.mideleg) | (val & state.mideleg));
+    case CSR_SIE:
+      return set_csr(CSR_MIE,
+                     (state.mie & ~state.mideleg) | (val & state.mideleg));
     case CSR_SEPC: state.sepc = val; break;
     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
     case CSR_SPTBR: state.sptbr = val; break;
@@ -361,13 +344,10 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_SCAUSE: state.scause = val; break;
     case CSR_SBADADDR: state.sbadaddr = val; break;
     case CSR_MEPC: state.mepc = val; break;
+    case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
     case CSR_MSCRATCH: state.mscratch = val; break;
     case CSR_MCAUSE: state.mcause = val; break;
     case CSR_MBADADDR: state.mbadaddr = val; break;
-    case CSR_MTIMECMP:
-      state.mip &= ~MIP_MTIP;
-      state.mtimecmp = val;
-      break;
     case CSR_MTOHOST:
       if (state.tohost == 0)
         state.tohost = val;
@@ -424,10 +404,8 @@ reg_t processor_t::get_csr(int which)
     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
-    case CSR_MTIME: return sim->rtc;
     case CSR_MCYCLE: return state.minstret;
     case CSR_MINSTRET: return state.minstret;
-    case CSR_MTIMEH: if (xlen > 32) break; else return sim->rtc >> 32;
     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
     case CSR_SSTATUS: {
@@ -439,8 +417,8 @@ reg_t processor_t::get_csr(int which)
         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
       return sstatus;
     }
-    case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
-    case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
+    case CSR_SIP: return state.mip & state.mideleg;
+    case CSR_SIE: return state.mie & state.mideleg;
     case CSR_SEPC: return state.sepc;
     case CSR_SBADADDR: return state.sbadaddr;
     case CSR_STVEC: return state.stvec;
@@ -459,13 +437,12 @@ reg_t processor_t::get_csr(int which)
     case CSR_MSCRATCH: return state.mscratch;
     case CSR_MCAUSE: return state.mcause;
     case CSR_MBADADDR: return state.mbadaddr;
-    case CSR_MTIMECMP: return state.mtimecmp;
     case CSR_MISA: return isa;
     case CSR_MARCHID: return 0;
     case CSR_MIMPID: return 0;
     case CSR_MVENDORID: return 0;
     case CSR_MHARTID: return id;
-    case CSR_MTVEC: return DEFAULT_MTVEC;
+    case CSR_MTVEC: return state.mtvec;
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case CSR_MTOHOST:
@@ -474,24 +451,6 @@ reg_t processor_t::get_csr(int which)
     case CSR_MFROMHOST:
       sim->get_htif()->tick(); // not necessary, but faster
       return state.fromhost;
-    case CSR_MCFGADDR: return sim->memsz;
-    case CSR_UARCH0:
-    case CSR_UARCH1:
-    case CSR_UARCH2:
-    case CSR_UARCH3:
-    case CSR_UARCH4:
-    case CSR_UARCH5:
-    case CSR_UARCH6:
-    case CSR_UARCH7:
-    case CSR_UARCH8:
-    case CSR_UARCH9:
-    case CSR_UARCH10:
-    case CSR_UARCH11:
-    case CSR_UARCH12:
-    case CSR_UARCH13:
-    case CSR_UARCH14:
-    case CSR_UARCH15:
-      return 0;
   }
   throw trap_illegal_instruction();
 }