#include "extension.h"
#include "common.h"
#include "config.h"
-#include "sim.h"
+#include "simif.h"
#include "mmu.h"
#include "disasm.h"
-#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#undef STATE
#define STATE state
-processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
+processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
bool halt_on_reset)
- : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
+ : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
+ halt_on_reset(halt_on_reset), last_pc(1), executions(1)
{
+ disassembler = new disassembler_t(max_xlen);
parse_isa_string(isa);
register_base_instructions();
mmu = new mmu_t(sim, this);
- disassembler = new disassembler_t(max_xlen);
reset();
}
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
- const char* all_subsets = "imafdc";
+ const char* all_subsets = "imafdqc";
max_xlen = 64;
- isa = reg_t(2) << 62;
+ state.misa = reg_t(2) << 62;
if (strncmp(p, "rv32", 4) == 0)
- max_xlen = 32, isa = reg_t(1) << 30, p += 4;
+ max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
p += 2;
if (!*p) {
- p = all_subsets;
+ p = "imafdc";
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
}
isa_string = "rv" + std::to_string(max_xlen) + p;
- isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
- isa |= 1L << ('u' - 'a'); // advertise support for user mode
+ state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+ state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
while (*p) {
- isa |= 1L << (*p - 'a');
+ state.misa |= 1L << (*p - 'a');
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
- // advertise support for supervisor and user modes
- isa |= 1L << ('s' - 'a');
- isa |= 1L << ('u' - 'a');
+ if (supports_extension('Q') && !supports_extension('D'))
+ bad_isa_string(str);
+
+ if (supports_extension('Q') && max_xlen < 64)
+ bad_isa_string(str);
+
+ max_isa = state.misa;
}
-void state_t::reset()
+void state_t::reset(reg_t max_isa)
{
memset(this, 0, sizeof(*this));
+ misa = max_isa;
prv = PRV_M;
pc = DEFAULT_RSTVEC;
- mtvec = DEFAULT_MTVEC;
- load_reservation = -1;
tselect = 0;
for (unsigned int i = 0; i < num_triggers; i++)
mcontrol[i].type = 2;
void processor_t::reset()
{
- state.reset();
+ state.reset(max_isa);
state.dcsr.halt = halt_on_reset;
halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
ext->reset(); // reset the extension
-}
-void processor_t::raise_interrupt(reg_t which)
-{
- throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
+ if (sim)
+ sim->proc_reset(id);
}
// Count number of contiguous 0 bits starting from the LSB.
return res;
}
-void processor_t::take_interrupt()
+void processor_t::take_interrupt(reg_t pending_interrupts)
{
- reg_t pending_interrupts = state.mip & state.mie;
-
reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
- enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
+ // M-ints have highest priority; consider S-ints only if no M-ints pending
+ if (enabled_interrupts == 0)
+ enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
+
+ if (state.dcsr.cause == 0 && enabled_interrupts) {
+ // nonstandard interrupts have highest priority
+ if (enabled_interrupts >> IRQ_M_EXT)
+ enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
+ // external interrupts have next-highest priority
+ else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
+ enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
+ // software interrupts have next-highest priority
+ else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
+ enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
+ // timer interrupts have next-highest priority
+ else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
+ enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
+ else
+ abort();
+
+ throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
+ }
+}
- if (enabled_interrupts)
- raise_interrupt(ctz(enabled_interrupts));
+static int xlen_to_uxl(int xlen)
+{
+ if (xlen == 32)
+ return 1;
+ if (xlen == 64)
+ return 2;
+ abort();
}
-void processor_t::set_privilege(reg_t prv)
+reg_t processor_t::legalize_privilege(reg_t prv)
{
assert(prv <= PRV_M);
- if (prv == PRV_H)
- prv = PRV_U;
+
+ if (!supports_extension('U'))
+ return PRV_M;
+
+ if (prv == PRV_H || !supports_extension('S'))
+ return PRV_U;
+
+ return prv;
+}
+
+void processor_t::set_privilege(reg_t prv)
+{
mmu->flush_tlb();
- state.prv = prv;
+ state.prv = legalize_privilege(prv);
}
void processor_t::enter_debug_mode(uint8_t cause)
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc = DEBUG_ROM_START;
+ state.pc = DEBUG_ROM_ENTRY;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
if (debug) {
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
- if (t.has_badaddr())
- fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
- t.get_badaddr());
+ if (t.has_tval())
+ fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id,
+ t.get_tval());
+ }
+
+ if (state.dcsr.cause) {
+ if (t.cause() == CAUSE_BREAKPOINT) {
+ state.pc = DEBUG_ROM_ENTRY;
+ } else {
+ state.pc = DEBUG_ROM_TVEC;
+ }
+ return;
}
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
- (state.prv == PRV_H && state.dcsr.ebreakh) ||
(state.prv == PRV_S && state.dcsr.ebreaks) ||
(state.prv == PRV_U && state.dcsr.ebreaku))) {
enter_debug_mode(DCSR_CAUSE_SWBP);
return;
}
- if (state.dcsr.cause) {
- state.pc = DEBUG_ROM_EXCEPTION;
- return;
- }
-
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
reg_t deleg = state.medeleg;
- if (bit & ((reg_t)1 << (max_xlen-1)))
+ bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
+ if (interrupt)
deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
// handle the trap in S-mode
state.pc = state.stvec;
state.scause = t.cause();
state.sepc = epc;
- if (t.has_badaddr())
- state.sbadaddr = t.get_badaddr();
+ state.stval = t.get_tval();
reg_t s = state.mstatus;
- s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
+ s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, state.prv);
s = set_field(s, MSTATUS_SIE, 0);
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- state.pc = state.mtvec;
+ reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
+ state.pc = (state.mtvec & ~(reg_t)1) + vector;
state.mepc = epc;
state.mcause = t.cause();
- if (t.has_badaddr())
- state.mbadaddr = t.get_badaddr();
+ state.mtval = t.get_tval();
reg_t s = state.mstatus;
- s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
+ s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
s = set_field(s, MSTATUS_MPP, state.prv);
s = set_field(s, MSTATUS_MIE, 0);
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_M);
}
-
- yield_load_reservation();
}
void processor_t::disasm(insn_t insn)
{
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
- fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
- id, state.pc, bits, disassembler->disassemble(insn).c_str());
-}
+ if (last_pc != state.pc || last_bits != bits) {
+ if (executions != 1) {
+ fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
+ }
-static bool validate_vm(int max_xlen, reg_t vm)
-{
- if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
- return true;
- if (max_xlen == 32 && vm == VM_SV32)
- return true;
- return vm == VM_MBARE;
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+ id, state.pc, bits, disassembler->disassemble(insn).c_str());
+ last_pc = state.pc;
+ last_bits = bits;
+ executions = 1;
+ } else {
+ executions++;
+ }
}
int processor_t::paddr_bits()
break;
case CSR_MSTATUS: {
if ((val ^ state.mstatus) &
- (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
+ (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
- | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
- | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
+ | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
+ | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
+ | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
+ (ext ? MSTATUS_XS : 0);
- if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
- mask |= MSTATUS_VM;
+ reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
+ state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
+ if (supports_extension('S'))
+ mask |= MSTATUS_SPP;
state.mstatus = (state.mstatus & ~mask) | (val & mask);
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
- // spike supports the notion of xlen < max_xlen, but current priv spec
- // doesn't provide a mechanism to run RV32 software on an RV64 machine
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
+ state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
+ // U-XLEN == S-XLEN == M-XLEN
xlen = max_xlen;
break;
}
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask =
+ (1 << CAUSE_MISALIGNED_FETCH) |
+ (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_USER_ECALL) |
+ (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) |
+ (1 << CAUSE_STORE_PAGE_FAULT);
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
- case CSR_MUCOUNTEREN:
- state.mucounteren = val & 7;
+ case CSR_MINSTRET:
+ case CSR_MCYCLE:
+ if (xlen == 32)
+ state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
+ else
+ state.minstret = val;
+ // The ISA mandates that if an instruction writes instret, the write
+ // takes precedence over the increment to instret. However, Spike
+ // unconditionally increments instret after executing an instruction.
+ // Correct for this artifact by decrementing instret here.
+ state.minstret--;
+ break;
+ case CSR_MINSTRETH:
+ case CSR_MCYCLEH:
+ state.minstret = (val << 32) | (state.minstret << 32 >> 32);
+ state.minstret--; // See comment above.
break;
- case CSR_MSCOUNTEREN:
- state.mscounteren = val & 7;
+ case CSR_SCOUNTEREN:
+ state.scounteren = val;
+ break;
+ case CSR_MCOUNTEREN:
+ state.mcounteren = val;
break;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_PUM;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
- case CSR_SIP:
- return set_csr(CSR_MIP,
- (state.mip & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SIP: {
+ reg_t mask = MIP_SSIP & state.mideleg;
+ return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
+ }
case CSR_SIE:
return set_csr(CSR_MIE,
(state.mie & ~state.mideleg) | (val & state.mideleg));
- case CSR_SPTBR: {
- // upper bits of sptbr are the ASID; we only support ASID = 0
- state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
+ case CSR_SATP: {
+ mmu->flush_tlb();
+ if (max_xlen == 32)
+ state.satp = val & (SATP32_PPN | SATP32_MODE);
+ if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
+ get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
+ get_field(val, SATP64_MODE) == SATP_MODE_SV48))
+ state.satp = val & (SATP64_PPN | SATP64_MODE);
break;
}
- case CSR_SEPC: state.sepc = val; break;
+ case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_SCAUSE: state.scause = val; break;
- case CSR_SBADADDR: state.sbadaddr = val; break;
- case CSR_MEPC: state.mepc = val; break;
- case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
+ case CSR_STVAL: state.stval = val; break;
+ case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
+ case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
- case CSR_MBADADDR: state.mbadaddr = val; break;
+ case CSR_MTVAL: state.mtval = val; break;
+ case CSR_MISA: {
+ // the write is ignored if increasing IALIGN would misalign the PC
+ if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
+ break;
+
+ if (!(val & (1L << ('F' - 'A'))))
+ val &= ~(1L << ('D' - 'A'));
+
+ // allow MAFDC bits in MISA to be modified
+ reg_t mask = 0;
+ mask |= 1L << ('M' - 'A');
+ mask |= 1L << ('A' - 'A');
+ mask |= 1L << ('F' - 'A');
+ mask |= 1L << ('D' - 'A');
+ mask |= 1L << ('C' - 'A');
+ mask &= max_isa;
+
+ state.misa = (val & mask) | (state.misa & ~mask);
+ break;
+ }
case CSR_TSELECT:
if (val < state.num_triggers) {
state.tselect = val;
{
mcontrol_t *mc = &state.mcontrol[state.tselect];
if (mc->dmode && !state.dcsr.cause) {
- throw trap_illegal_instruction();
+ break;
}
mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
mc->select = get_field(val, MCONTROL_SELECT);
mc->store = get_field(val, MCONTROL_STORE);
mc->load = get_field(val, MCONTROL_LOAD);
// Assume we're here because of csrw.
+ if (mc->execute)
+ mc->timing = 0;
trigger_updated();
}
break;
case CSR_TDATA2:
+ if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
+ break;
+ }
if (state.tselect < state.num_triggers) {
state.tdata2[state.tselect] = val;
}
state.dcsr.halt = get_field(val, DCSR_HALT);
break;
case CSR_DPC:
- state.dpc = val;
+ state.dpc = val & ~(reg_t)1;
break;
case CSR_DSCRATCH:
state.dscratch = val;
reg_t processor_t::get_csr(int which)
{
+ uint32_t ctr_en = -1;
+ if (state.prv < PRV_M)
+ ctr_en &= state.mcounteren;
+ if (state.prv < PRV_S)
+ ctr_en &= state.scounteren;
+ bool ctr_ok = (ctr_en >> (which & 31)) & 1;
+
+ if (ctr_ok) {
+ if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
+ return 0;
+ if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
+ return 0;
+ }
+ if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
+ return 0;
+ if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
+ return 0;
+ if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
+ return 0;
+
switch (which)
{
case CSR_FFLAGS:
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
- case CSR_TIME:
case CSR_INSTRET:
case CSR_CYCLE:
- if ((state.mucounteren >> (which & (xlen-1))) & 1)
- return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+ if (ctr_ok)
+ return state.minstret;
+ break;
+ case CSR_MINSTRET:
+ case CSR_MCYCLE:
+ return state.minstret;
+ case CSR_INSTRETH:
+ case CSR_CYCLEH:
+ if (ctr_ok && xlen == 32)
+ return state.minstret >> 32;
break;
- case CSR_STIME:
- case CSR_SINSTRET:
- case CSR_SCYCLE:
- if ((state.mscounteren >> (which & (xlen-1))) & 1)
- return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+ case CSR_MINSTRETH:
+ case CSR_MCYCLEH:
+ if (xlen == 32)
+ return state.minstret >> 32;
break;
- case CSR_MUCOUNTEREN: return state.mucounteren;
- case CSR_MSCOUNTEREN: return state.mscounteren;
- case CSR_MUCYCLE_DELTA: return 0;
- case CSR_MUTIME_DELTA: return 0;
- case CSR_MUINSTRET_DELTA: return 0;
- case CSR_MSCYCLE_DELTA: return 0;
- case CSR_MSTIME_DELTA: return 0;
- case CSR_MSINSTRET_DELTA: return 0;
- case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
- case CSR_MCYCLE: return state.minstret;
- case CSR_MINSTRET: return state.minstret;
- case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
- case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_SCOUNTEREN: return state.scounteren;
+ case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_PUM;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)
}
case CSR_SIP: return state.mip & state.mideleg;
case CSR_SIE: return state.mie & state.mideleg;
- case CSR_SEPC: return state.sepc;
- case CSR_SBADADDR: return state.sbadaddr;
+ case CSR_SEPC: return state.sepc & pc_alignment_mask();
+ case CSR_STVAL: return state.stval;
case CSR_STVEC: return state.stvec;
case CSR_SCAUSE:
if (max_xlen > xlen)
return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
return state.scause;
- case CSR_SPTBR: return state.sptbr;
+ case CSR_SATP:
+ if (get_field(state.mstatus, MSTATUS_TVM))
+ require_privilege(PRV_M);
+ return state.satp;
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
case CSR_MIE: return state.mie;
- case CSR_MEPC: return state.mepc;
+ case CSR_MEPC: return state.mepc & pc_alignment_mask();
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
- case CSR_MBADADDR: return state.mbadaddr;
- case CSR_MISA: return isa;
+ case CSR_MTVAL: return state.mtval;
+ case CSR_MISA: return state.misa;
case CSR_MARCHID: return 0;
case CSR_MIMPID: return 0;
case CSR_MVENDORID: return 0;
return 0;
}
break;
+ case CSR_TDATA3: return 0;
case CSR_DCSR:
{
uint32_t v = 0;
v = set_field(v, DCSR_XDEBUGVER, 1);
- v = set_field(v, DCSR_NDRESET, 0);
- v = set_field(v, DCSR_FULLRESET, 0);
- v = set_field(v, DCSR_PRV, state.dcsr.prv);
- v = set_field(v, DCSR_STEP, state.dcsr.step);
- v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
- v = set_field(v, DCSR_STOPCYCLE, 0);
- v = set_field(v, DCSR_STOPTIME, 0);
v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
- v = set_field(v, DCSR_HALT, state.dcsr.halt);
+ v = set_field(v, DCSR_STOPCYCLE, 0);
+ v = set_field(v, DCSR_STOPTIME, 0);
v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+ v = set_field(v, DCSR_STEP, state.dcsr.step);
+ v = set_field(v, DCSR_PRV, state.dcsr.prv);
return v;
}
case CSR_DPC:
- return state.dpc;
+ return state.dpc & pc_alignment_mask();
case CSR_DSCRATCH:
return state.dscratch;
}
- throw trap_illegal_instruction();
+ throw trap_illegal_instruction(0);
}
reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
{
- throw trap_illegal_instruction();
+ throw trap_illegal_instruction(0);
}
insn_func_t processor_t::decode_insn(insn_t insn)
bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
+ switch (addr)
+ {
+ case 0:
+ if (len <= 4) {
+ memset(bytes, 0, len);
+ bytes[0] = get_field(state.mip, MIP_MSIP);
+ return true;
+ }
+ break;
+ }
+
return false;
}
switch (addr)
{
case 0:
- state.mip &= ~MIP_MSIP;
- if (bytes[0] & 1)
- state.mip |= MIP_MSIP;
- return true;
-
- default:
- return false;
+ if (len <= 4) {
+ state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
+ return true;
+ }
+ break;
}
+
+ return false;
}
void processor_t::trigger_updated()