#include "mmu.h"
#include "htif.h"
#include "disasm.h"
+#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#define STATE state
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
- : sim(sim), ext(NULL), disassembler(new disassembler_t),
- id(id), run(false), debug(false), halted(false), single_step(false)
+ : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
+ id(id), run(false)
{
parse_isa_string(isa);
ext->set_debug(value);
}
-void processor_t::set_halted(bool value, halt_reason_t reason)
-{
- halted = value;
- halt_reason = reason;
-}
-
-void processor_t::set_single_step(bool value)
-{
- single_step = value;
-}
-
void processor_t::set_histogram(bool value)
{
histogram_enabled = value;
state.prv = prv;
}
+void processor_t::enter_debug_mode(uint8_t cause)
+{
+ fprintf(stderr, "enter_debug_mode(%d)\n", cause);
+ state.dcsr.cause = cause;
+ state.dcsr.prv = state.prv;
+ state.prv = PRV_M;
+ state.dpc = state.pc;
+ state.pc = DEBUG_ROM_START;
+ debug = true; // TODO
+}
+
void processor_t::take_trap(trap_t& t, reg_t epc)
{
- if (debug)
+ if (debug) {
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
+ if (t.has_badaddr())
+ fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
+ t.get_badaddr());
+ }
- if (t.cause() == CAUSE_BREAKPOINT) {
- // TODO: Only do this if there is a debugger attached.
- set_halted(true, HR_SWBP);
+ if (t.cause() == CAUSE_BREAKPOINT &&
+ sim->gdbserver && sim->gdbserver->connected()) {
+ enter_debug_mode(DCSR_CAUSE_SWBP);
return;
}
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- state.pc = state.mtvec;
+ if (state.dcsr.cause) {
+ state.pc = DEBUG_ROM_EXCEPTION;
+ } else {
+ state.pc = state.mtvec;
+ }
state.mcause = t.cause();
state.mepc = epc;
if (t.has_badaddr())
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
+ case DCSR_ADDRESS:
+ // TODO: Use get_field style
+ state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
+ state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
+ // TODO: ndreset and fullreset
+ state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
+ state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
+ state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
+ state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
+ state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
+ break;
+ case DPC_ADDRESS:
+ state.dpc = val;
+ break;
+ case DSCRATCH_ADDRESS:
+ state.dscratch = val;
+ break;
}
}
case CSR_MTVEC: return state.mtvec;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
+ case DCSR_ADDRESS:
+ {
+ uint32_t value =
+ (1 << DCSR_XDEBUGVER_OFFSET) |
+ (0 << DCSR_HWBPCOUNT_OFFSET) |
+ (0 << DCSR_NDRESET_OFFSET) |
+ (0 << DCSR_FULLRESET_OFFSET) |
+ (state.dcsr.prv << DCSR_PRV_OFFSET) |
+ (state.dcsr.step << DCSR_STEP_OFFSET) |
+ (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
+ (0 << DCSR_STOPCYCLE_OFFSET) |
+ (0 << DCSR_STOPTIME_OFFSET) |
+ (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
+ (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
+ (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
+ (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
+ (state.dcsr.halt << DCSR_HALT_OFFSET) |
+ (state.dcsr.cause << DCSR_CAUSE_OFFSET);
+ return value;
+ }
+ case DPC_ADDRESS:
+ return state.dpc;
+ case DSCRATCH_ADDRESS:
+ return state.dscratch;
}
throw trap_illegal_instruction();
}