Implement single memory read access.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9b97120cc1886d3994bcc0de932c8cd6cc00c176..f09eea8f6c64e9289c52483f5595b008d261bc0d 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -206,9 +206,13 @@ void processor_t::enter_debug_mode(uint8_t cause)
 
 void processor_t::take_trap(trap_t& t, reg_t epc)
 {
-  if (debug)
+  if (debug) {
     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
             id, t.name(), epc);
+    if (t.has_badaddr())
+      fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
+          t.get_badaddr());
+  }
 
   if (t.cause() == CAUSE_BREAKPOINT &&
           sim->gdbserver && sim->gdbserver->connected()) {
@@ -236,7 +240,11 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     set_csr(CSR_MSTATUS, s);
     set_privilege(PRV_S);
   } else {
-    state.pc = state.mtvec;
+    if (state.dcsr.cause) {
+      state.pc = DEBUG_ROM_EXCEPTION;
+    } else {
+      state.pc = state.mtvec;
+    }
     state.mcause = t.cause();
     state.mepc = epc;
     if (t.has_badaddr())
@@ -470,7 +478,8 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case DCSR_ADDRESS:
-      return
+      {
+        uint32_t value =
           (1 << DCSR_XDEBUGVER_OFFSET) |
           (0 << DCSR_HWBPCOUNT_OFFSET) |
           (0 << DCSR_NDRESET_OFFSET) |
@@ -486,6 +495,8 @@ reg_t processor_t::get_csr(int which)
           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
           (state.dcsr.halt << DCSR_HALT_OFFSET) |
           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
+        return value;
+      }
     case DPC_ADDRESS:
       return state.dpc;
     case DSCRATCH_ADDRESS: