Add dret.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7c5c0fbfac8c583ff47fa00b0576560295d918bb..f98d0a090e139deab65d1a61f7ca7009864d0cce 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -8,6 +8,7 @@
 #include "mmu.h"
 #include "htif.h"
 #include "disasm.h"
+#include "gdbserver.h"
 #include <cinttypes>
 #include <cmath>
 #include <cstdlib>
@@ -21,8 +22,8 @@
 #define STATE state
 
 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
-  : sim(sim), ext(NULL), disassembler(new disassembler_t),
-    id(id), run(false), debug(false)
+  : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
+    id(id), run(false)
 {
   parse_isa_string(isa);
 
@@ -119,11 +120,6 @@ void state_t::reset()
   load_reservation = -1;
 }
 
-void processor_t::set_debug_int()
-{
-  state.dcsr.debugint = true;
-}
-
 void processor_t::set_debug(bool value)
 {
   debug = value;
@@ -202,7 +198,7 @@ void processor_t::enter_debug_mode(uint8_t cause)
   fprintf(stderr, "enter_debug_mode(%d)\n", cause);
   state.dcsr.cause = cause;
   state.dcsr.prv = state.prv;
-  state.prv = PRV_M;
+  set_privilege(PRV_M);
   state.dpc = state.pc;
   state.pc = DEBUG_ROM_START;
   debug = true; // TODO
@@ -210,9 +206,13 @@ void processor_t::enter_debug_mode(uint8_t cause)
 
 void processor_t::take_trap(trap_t& t, reg_t epc)
 {
-  if (debug)
+  if (debug) {
     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
             id, t.name(), epc);
+    if (t.has_badaddr())
+      fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
+          t.get_badaddr());
+  }
 
   if (t.cause() == CAUSE_BREAKPOINT &&
           sim->gdbserver && sim->gdbserver->connected()) {
@@ -240,7 +240,11 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     set_csr(CSR_MSTATUS, s);
     set_privilege(PRV_S);
   } else {
-    state.pc = state.mtvec;
+    if (state.dcsr.cause) {
+      state.pc = DEBUG_ROM_EXCEPTION;
+    } else {
+      state.pc = state.mtvec;
+    }
     state.mcause = t.cause();
     state.mepc = epc;
     if (t.has_badaddr())
@@ -474,14 +478,15 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case DCSR_ADDRESS:
-      return
+      {
+        uint32_t value =
           (1 << DCSR_XDEBUGVER_OFFSET) |
           (0 << DCSR_HWBPCOUNT_OFFSET) |
           (0 << DCSR_NDRESET_OFFSET) |
           (0 << DCSR_FULLRESET_OFFSET) |
           (state.dcsr.prv << DCSR_PRV_OFFSET) |
           (state.dcsr.step << DCSR_STEP_OFFSET) |
-          (state.dcsr.debugint << DCSR_DEBUGINT_OFFSET) |
+          (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
           (0 << DCSR_STOPCYCLE_OFFSET) |
           (0 << DCSR_STOPTIME_OFFSET) |
           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
@@ -490,6 +495,8 @@ reg_t processor_t::get_csr(int which)
           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
           (state.dcsr.halt << DCSR_HALT_OFFSET) |
           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
+        return value;
+      }
     case DPC_ADDRESS:
       return state.dpc;
     case DSCRATCH_ADDRESS: