#include "mmu.h"
#include "htif.h"
#include "disasm.h"
+#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#define STATE state
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
- : sim(sim), ext(NULL), disassembler(new disassembler_t),
- id(id), run(false), debug(false)
+ : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
+ id(id), run(false)
{
parse_isa_string(isa);
memset(this, 0, sizeof(*this));
prv = PRV_M;
pc = DEFAULT_RSTVEC;
+ mtvec = DEFAULT_MTVEC;
load_reservation = -1;
}
state.prv = prv;
}
+void processor_t::enter_debug_mode(uint8_t cause)
+{
+ fprintf(stderr, "enter_debug_mode(%d)\n", cause);
+ state.dcsr.cause = cause;
+ state.dcsr.prv = state.prv;
+ set_privilege(PRV_M);
+ state.dpc = state.pc;
+ state.pc = DEBUG_ROM_START;
+ debug = true; // TODO
+}
+
void processor_t::take_trap(trap_t& t, reg_t epc)
{
- if (debug)
+ if (debug) {
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
+ if (t.has_badaddr())
+ fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
+ t.get_badaddr());
+ }
+
+ if (t.cause() == CAUSE_BREAKPOINT &&
+ sim->gdbserver && sim->gdbserver->connected()) {
+ enter_debug_mode(DCSR_CAUSE_SWBP);
+ return;
+ }
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- state.pc = state.mtvec;
+ if (state.dcsr.cause) {
+ state.pc = DEBUG_ROM_EXCEPTION;
+ } else {
+ state.pc = state.mtvec;
+ }
state.mcause = t.cause();
state.mepc = epc;
if (t.has_badaddr())
void processor_t::set_csr(int which, reg_t val)
{
val = zext_xlen(val);
- reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP);
+ reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
switch (which)
{
break;
}
case CSR_MIP: {
- reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP;
+ reg_t mask = MIP_SSIP | MIP_STIP;
state.mip = (state.mip & ~mask) | (val & mask);
break;
}
- case CSR_MIPI:
- state.mip = set_field(state.mip, MIP_MSIP, val & 1);
- break;
case CSR_MIE:
state.mie = (state.mie & ~all_ints) | (val & all_ints);
break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
- case CSR_MTOHOST:
- if (state.tohost == 0)
- state.tohost = val;
+ case DCSR_ADDRESS:
+ // TODO: Use get_field style
+ state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
+ state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
+ // TODO: ndreset and fullreset
+ state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
+ state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
+ state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
+ state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
+ state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
break;
- case CSR_MFROMHOST:
- state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
- state.fromhost = val;
+ case DPC_ADDRESS:
+ state.dpc = val;
+ break;
+ case DSCRATCH_ADDRESS:
+ state.dscratch = val;
break;
}
}
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
- case CSR_MIPI: return 0;
case CSR_MIE: return state.mie;
case CSR_MEPC: return state.mepc;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MTVEC: return state.mtvec;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
- case CSR_MTOHOST:
- sim->get_htif()->tick(); // not necessary, but faster
- return state.tohost;
- case CSR_MFROMHOST:
- sim->get_htif()->tick(); // not necessary, but faster
- return state.fromhost;
+ case DCSR_ADDRESS:
+ {
+ uint32_t value =
+ (1 << DCSR_XDEBUGVER_OFFSET) |
+ (0 << DCSR_HWBPCOUNT_OFFSET) |
+ (0 << DCSR_NDRESET_OFFSET) |
+ (0 << DCSR_FULLRESET_OFFSET) |
+ (state.dcsr.prv << DCSR_PRV_OFFSET) |
+ (state.dcsr.step << DCSR_STEP_OFFSET) |
+ (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
+ (0 << DCSR_STOPCYCLE_OFFSET) |
+ (0 << DCSR_STOPTIME_OFFSET) |
+ (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
+ (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
+ (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
+ (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
+ (state.dcsr.halt << DCSR_HALT_OFFSET) |
+ (state.dcsr.cause << DCSR_CAUSE_OFFSET);
+ return value;
+ }
+ case DPC_ADDRESS:
+ return state.dpc;
+ case DSCRATCH_ADDRESS:
+ return state.dscratch;
}
throw trap_illegal_instruction();
}
bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
- try {
- auto res = get_csr(addr / (max_xlen / 8));
- memcpy(bytes, &res, len);
- return true;
- } catch (trap_illegal_instruction& t) {
- return false;
- }
+ return false;
}
bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
{
- try {
- reg_t value = 0;
- memcpy(&value, bytes, len);
- set_csr(addr / (max_xlen / 8), value);
- return true;
- } catch (trap_illegal_instruction& t) {
- return false;
+ switch (addr)
+ {
+ case 0:
+ state.mip &= ~MIP_MSIP;
+ if (bytes[0] & 1)
+ state.mip |= MIP_MSIP;
+ return true;
+
+ default:
+ return false;
}
}
projects / riscv-isa-sim.git / blobdiff