#include <cstring>
#include "trap.h"
#include "mmu.h"
+#include "icsim.h"
+
+#define MAX_UTS 2048
class sim_t;
{
public:
processor_t(sim_t* _sim, char* _mem, size_t _memsz);
- void init(uint32_t _id);
+ ~processor_t();
+ void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
void step(size_t n, bool noisy);
+ void deliver_ipi();
private:
sim_t* sim;
// architected state
- reg_t R[NGPR];
- freg_t FR[NFPR];
+ reg_t XPR[NXPR];
+ freg_t FPR[NFPR];
// privileged control registers
reg_t pc;
reg_t epc;
reg_t badvaddr;
- reg_t ebase;
+ reg_t cause;
+ reg_t evec;
reg_t tohost;
reg_t fromhost;
reg_t pcr_k0;
reg_t pcr_k1;
uint32_t id;
uint32_t sr;
+ uint32_t count;
+ uint32_t compare;
+
+ bool run;
// unprivileged control registers
- uint32_t tid;
uint32_t fsr;
- // 32-bit or 64-bit mode (redundant with sr)
- int gprlen;
+ // # of bits in an XPR (32 or 64). (redundant with sr)
+ int xprlen;
// shared memory
mmu_t mmu;
// counters
- reg_t counters[32];
+ reg_t cycle;
// functions
+ void reset();
+ void take_interrupt();
void set_sr(uint32_t val);
void set_fsr(uint32_t val);
void take_trap(trap_t t, bool noisy);
void disasm(insn_t insn, reg_t pc);
+ // vector stuff
+ void vcfg();
+ void setvl(int vlapp);
+
+ reg_t vecbanks;
+ uint32_t vecbanks_count;
+
+ bool utmode;
+ int utidx;
+ int vlmax;
+ int vl;
+ int nxfpr_bank;
+ int nxpr_use;
+ int nfpr_use;
+ processor_t* uts[MAX_UTS];
+
+ // cache sim
+ icsim_t* icsim;
+ icsim_t* dcsim;
+ icsim_t* itlbsim;
+ icsim_t* dtlbsim;
+
friend class sim_t;
+
+ #include "dispatch_decl.h"
};
#endif