Take interrupts as soon as interrupts are enabled

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 4189fea8615f68271ff120b6c2b15791a79f002a..1d497d0c8ef5f5678d2bc90e7f5405d3eee0075b 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -45,16 +45,19 @@ struct state_t
   reg_t mbadaddr;
   reg_t mscratch;
   reg_t mcause;
+  reg_t mtime;
+  reg_t mie;
+  reg_t mip;
   reg_t sepc;
   reg_t sbadaddr;
   reg_t sscratch;
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
+  reg_t sutime_delta;
   reg_t tohost;
   reg_t fromhost;
-  reg_t scount;
-  bool stip;
+  bool serialized; // whether timer CSRs are in a well-defined state
   uint32_t stimecmp;
   uint32_t fflags;
   uint32_t frm;
@@ -70,7 +73,7 @@ struct state_t
 class processor_t
 {
 public:
-  processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
+  processor_t(const char* isa, sim_t* sim, uint32_t id);
   ~processor_t();
 
   void set_debug(bool value);
@@ -85,6 +88,9 @@ public:
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
   extension_t* get_extension() { return ext; }
+  bool supports_extension(unsigned char ext) {
+    return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
+  }
   void push_privilege_stack();
   void pop_privilege_stack();
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
@@ -99,12 +105,13 @@ private:
   extension_t* ext;
   disassembler_t* disassembler;
   state_t state;
+  reg_t cpuid;
   uint32_t id;
+  int max_xlen;
   int xlen;
   bool run; // !reset
   bool debug;
   bool histogram_enabled;
-  bool serialized;
 
   std::vector<insn_desc_t> instructions;
   std::vector<insn_desc_t*> opcode_map;
@@ -112,14 +119,14 @@ private:
   std::map<size_t,size_t> pc_histogram;
 
   void take_interrupt(); // take a trap if any interrupts are pending
-  void serialize(); // collapse into defined architectural state
-  reg_t take_trap(trap_t& t, reg_t epc); // take an exception
+  void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
   friend class sim_t;
   friend class mmu_t;
   friend class extension_t;
 
+  void parse_isa_string(const char* isa);
   void build_opcode_map();
   insn_func_t decode_insn(insn_t insn);
 };