Add (degenerate) performance counter facility

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 31d5f6ca7dd442ef3005e04a4832823bdfbbcf77..3f3d66b10849ab335a5234bd73745bf82434ec89 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -65,8 +65,8 @@ struct state_t
   reg_t mip;
   reg_t medeleg;
   reg_t mideleg;
-  reg_t mucounteren;
-  reg_t mscounteren;
+  uint32_t mucounteren;
+  uint32_t mscounteren;
   reg_t sepc;
   reg_t sbadaddr;
   reg_t sscratch;
@@ -121,6 +121,7 @@ public:
   void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
   void update_histogram(reg_t pc);
+  const disassembler_t* get_disassembler() { return disassembler; }
 
   void register_insn(insn_desc_t);
   void register_extension(extension_t*);