Merge remote-tracking branch 'origin/priv-1.10' into HEAD

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 7e9e932f7b13a8c5cd4cb3275c3a697913c6f0f1..4d94d5b42a9a181886c4a520fead3cd0edf67a97 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -191,6 +191,13 @@ public:
   bool debug;
   // When true, take the slow simulation path.
   bool slow_path();
+  bool halted() { return state.dcsr.cause ? true : false; }
+  bool halt_request;
+  // The unique debug rom address that this hart jumps to when entering debug
+  // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
+  uint32_t debug_rom_entry() {
+    return DEBUG_ROM_ENTRY + 4 * id;
+  }
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)