[xcc,pk,sim] Added first part of FP support
[riscv-isa-sim.git] / riscv / processor.h
index 33ca93921efcce200f7a3eba37dd6260530a2172..652fa07c6a4cc5b4ee2aaf8d06cc25f21a279140 100644 (file)
@@ -20,6 +20,7 @@ private:
 
   // architected state
   reg_t R[NGPR];
+  freg_t FR[NFPR];
   reg_t pc;
   reg_t epc;
   reg_t badvaddr;