#endif
};
+typedef enum {
+ HR_NONE,
+ HR_STEPPED, // A single step was completed
+ HR_SWBP, // sbreak was executed
+ HR_INTERRUPT, // Execution interrupted by debugger
+ HR_CMDLINE, // Command line requested that the processor start halted
+ HR_ATTACHED // Halted because a debugger attached
+} halt_reason_t;
+
// this class represents one processor in a RISC-V machine.
class processor_t : public abstract_device_t
{
~processor_t();
void set_debug(bool value);
+ void set_halted(bool value, halt_reason_t reason);
+ void set_single_step(bool value);
void set_histogram(bool value);
void reset(bool value);
void step(size_t n); // run for n cycles
reg_t isa;
std::string isa_string;
bool run; // !reset
+ // When true, display disassembly of each instruction that's executed.
bool debug;
+ // TODO: Should this just be rolled into `run`?
+ bool halted; // When true, no instructions are executed.
+ halt_reason_t halt_reason; // Why is halted true?
+ // When true, execute exactly one instruction (even if halted is true), then
+ // set halted to true and single_step to false.
+ bool single_step;
bool histogram_enabled;
std::vector<insn_desc_t> instructions;