Now you can halt/continue from gdb.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 7d71b315f042472c3b1ca4b52e711ad2ed0aa574..94e95939aebe547f492f8dd955beafeac6ec8e9c 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -45,22 +45,22 @@ struct state_t
   reg_t mstatus;
   reg_t mepc;
   reg_t mbadaddr;
-  reg_t mtimecmp;
   reg_t mscratch;
+  reg_t mtvec;
   reg_t mcause;
   reg_t minstret;
   reg_t mie;
   reg_t mip;
   reg_t medeleg;
   reg_t mideleg;
+  reg_t mucounteren;
+  reg_t mscounteren;
   reg_t sepc;
   reg_t sbadaddr;
   reg_t sscratch;
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
-  reg_t tohost;
-  reg_t fromhost;
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
@@ -81,6 +81,7 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
+  void set_halted(bool value);
   void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
@@ -118,7 +119,10 @@ private:
   reg_t isa;
   std::string isa_string;
   bool run; // !reset
+  // When true, display disassembly of each instruction that's executed.
   bool debug;
+  // TODO: Should this just be rolled into `run`?
+  bool halted;  // When true, no instructions are executed.
   bool histogram_enabled;
 
   std::vector<insn_desc_t> instructions;
@@ -134,7 +138,9 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
+  friend class rtc_t;
   friend class extension_t;
+  friend class gdbserver_t;
 
   void parse_isa_string(const char* isa);
   void build_opcode_map();