processor_t unfriends gdbserver_t.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 3adf9903471f24846420d92aa5da9f9b56f83cf0..9c2f7a66aa1da730fc72bcabeb54c983bbc1c831 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -31,6 +31,18 @@ struct commit_log_reg_t
   reg_t data;
 };
 
+typedef struct
+{
+  uint8_t prv;
+  bool step;
+  bool ebreakm;
+  bool ebreakh;
+  bool ebreaks;
+  bool ebreaku;
+  bool halt;
+  uint8_t cause;
+} dcsr_t;
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -61,6 +73,10 @@ struct state_t
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
+  reg_t dpc;
+  reg_t dscratch;
+  dcsr_t dcsr;
+
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
@@ -106,6 +122,9 @@ public:
   bool load(reg_t addr, size_t len, uint8_t* bytes);
   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 
+  // When true, display disassembly of each instruction that's executed.
+  bool debug;
+
 private:
   sim_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu
@@ -118,7 +137,6 @@ private:
   reg_t isa;
   std::string isa_string;
   bool run; // !reset
-  bool debug;
   bool histogram_enabled;
 
   std::vector<insn_desc_t> instructions;
@@ -132,11 +150,12 @@ private:
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
+  void enter_debug_mode(uint8_t cause);
+
   friend class sim_t;
   friend class mmu_t;
   friend class rtc_t;
   friend class extension_t;
-  friend class gdbserver_t;
 
   void parse_isa_string(const char* isa);
   void build_opcode_map();