Generate instruction decoder dynamically

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 1e007a8fbdbb1829bdfbb673feaa4687578dbbb4..c2d0ea5709a2939833abde117f69e50c16ddcd11 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_PROCESSOR_H
 #define _RISCV_PROCESSOR_H
 
@@ -5,6 +7,7 @@
 #include <cstring>
 #include "trap.h"
 #include "config.h"
+#include <map>
 
 #define MAX_UTS 2048
 
@@ -20,19 +23,25 @@ public:
   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
   ~processor_t();
 
+  void reset(bool value);
   void step(size_t n, bool noisy); // run for n cycles
   void deliver_ipi(); // register an interprocessor interrupt
+  bool running() { return run; }
+  void set_pcr(int which, reg_t val);
+  void set_interrupt(int which, bool on);
+  reg_t get_pcr(int which);
+  mmu_t* get_mmu() { return &mmu; }
+
+  void register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64);
 
 private:
   sim_t& sim;
   mmu_t& mmu; // main memory is always accessed via the mmu
 
   // user-visible architected state
-  reg_t XPR[NXPR];
-  freg_t FPR[NFPR];
   reg_t pc;
-
-  // counters
+  regfile_t<reg_t, NXPR, true> XPR;
+  regfile_t<freg_t, NFPR, false> FPR;
   reg_t cycle;
 
   // privileged control registers
@@ -41,26 +50,30 @@ private:
   reg_t evec;
   reg_t pcr_k0;
   reg_t pcr_k1;
-  uint32_t cause;
-  uint32_t interrupts_pending;
+  reg_t cause;
+  reg_t tohost;
+  reg_t fromhost;
   uint32_t id;
-  uint32_t sr; // only modify the status register using set_sr()
+  uint32_t sr; // only modify the status register using set_pcr()
   uint32_t fsr;
   uint32_t count;
   uint32_t compare;
 
-  // # of bits in an XPR (32 or 64). (redundant with sr)
-  int xprlen;
+  bool run; // !reset
 
-  // is this processor running? (deliver_ipi() sets this)
-  bool run;
+  struct opcode_map_entry_t
+  {
+    uint32_t match;
+    uint32_t mask;
+    insn_func_t rv32;
+    insn_func_t rv64;
+  };
+  unsigned opcode_bits;
+  std::multimap<uint32_t, opcode_map_entry_t> opcode_map;
 
-  // functions
-  void reset(); // resets architected state; halts processor if it was running
   void take_interrupt(); // take a trap if any interrupts are pending
-  void set_sr(uint32_t val); // set the status register
   void set_fsr(uint32_t val); // set the floating-point status register
-  void take_trap(trap_t t, bool noisy); // take an exception
+  void take_trap(reg_t t, bool noisy); // take an exception
   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
 
   // vector stuff
@@ -84,20 +97,28 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
+  friend class htif_isasim_t;
+
+  #define DECLARE_INSN(name, match, mask) \
+    reg_t rv32_ ## name(insn_t insn, reg_t pc); \
+    reg_t rv64_ ## name(insn_t insn, reg_t pc);
+  #include "opcodes.h"
+  #undef DECLARE_INSN
 
-  #include "dispatch.h"
+  insn_func_t decode_insn(insn_t insn);
+  reg_t illegal_instruction(insn_t insn, reg_t pc);
 };
 
 #ifndef RISCV_ENABLE_RVC
 # define set_pc(x) \
-  do { if((x) & (sizeof(insn_t)-1)) \
-       { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+  do { if ((x) & 3) \
+         throw trap_instruction_address_misaligned; \
        npc = (x); \
      } while(0)
 #else
 # define set_pc(x) \
-  do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
-       { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+  do { if ((x) & ((sr & SR_EC) ? 1 : 3)) \
+         throw trap_instruction_address_misaligned; \
        npc = (x); \
      } while(0)
 #endif