Generate instruction decoder dynamically

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index ce07d464c36052a934208cef696dba025bfdacc4..c2d0ea5709a2939833abde117f69e50c16ddcd11 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -1,72 +1,80 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_PROCESSOR_H
 #define _RISCV_PROCESSOR_H
 
 #include "decode.h"
 #include <cstring>
 #include "trap.h"
-#include "mmu.h"
-#include "icsim.h"
+#include "config.h"
+#include <map>
 
 #define MAX_UTS 2048
 
-#define DISPATCH_TABLE_SIZE 1024
 class processor_t;
+class mmu_t;
 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
-
 class sim_t;
 
+// this class represents one processor in a RISC-V machine.
 class processor_t
 {
 public:
-  processor_t(sim_t* _sim, mmu_t* _mmu);
+  processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
   ~processor_t();
-  void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
-  void step(size_t n, bool noisy);
-  void deliver_ipi();
+
+  void reset(bool value);
+  void step(size_t n, bool noisy); // run for n cycles
+  void deliver_ipi(); // register an interprocessor interrupt
+  bool running() { return run; }
+  void set_pcr(int which, reg_t val);
+  void set_interrupt(int which, bool on);
+  reg_t get_pcr(int which);
+  mmu_t* get_mmu() { return &mmu; }
+
+  void register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64);
 
 private:
-  sim_t* sim;
+  sim_t& sim;
+  mmu_t& mmu; // main memory is always accessed via the mmu
 
-  // architected state
-  reg_t XPR[NXPR];
-  freg_t FPR[NFPR];
+  // user-visible architected state
+  reg_t pc;
+  regfile_t<reg_t, NXPR, true> XPR;
+  regfile_t<freg_t, NFPR, false> FPR;
+  reg_t cycle;
 
   // privileged control registers
-  reg_t pc;
   reg_t epc;
   reg_t badvaddr;
-  reg_t cause;
   reg_t evec;
-  reg_t tohost;
-  reg_t fromhost;
   reg_t pcr_k0;
   reg_t pcr_k1;
+  reg_t cause;
+  reg_t tohost;
+  reg_t fromhost;
   uint32_t id;
-  uint32_t sr;
+  uint32_t sr; // only modify the status register using set_pcr()
+  uint32_t fsr;
   uint32_t count;
   uint32_t compare;
 
-  bool run;
-
-  // unprivileged control registers
-  uint32_t fsr;
-
-  // # of bits in an XPR (32 or 64). (redundant with sr)
-  int xprlen;
+  bool run; // !reset
 
-  // shared memory
-  mmu_t& mmu;
+  struct opcode_map_entry_t
+  {
+    uint32_t match;
+    uint32_t mask;
+    insn_func_t rv32;
+    insn_func_t rv64;
+  };
+  unsigned opcode_bits;
+  std::multimap<uint32_t, opcode_map_entry_t> opcode_map;
 
-  // counters
-  reg_t cycle;
-
-  // functions
-  void reset();
-  void take_interrupt();
-  void set_sr(uint32_t val);
-  void set_fsr(uint32_t val);
-  void take_trap(trap_t t, bool noisy);
-  void disasm(insn_t insn, reg_t pc);
+  void take_interrupt(); // take a trap if any interrupts are pending
+  void set_fsr(uint32_t val); // set the floating-point status register
+  void take_trap(reg_t t, bool noisy); // take an exception
+  void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
 
   // vector stuff
   void vcfg();
@@ -76,7 +84,7 @@ private:
   uint32_t vecbanks_count;
 
   bool utmode;
-  int utidx;
+  uint32_t utidx;
   int vlmax;
   int vl;
   int nxfpr_bank;
@@ -84,21 +92,35 @@ private:
   int nfpr_use;
   processor_t* uts[MAX_UTS];
 
-  // cache sim
-  icsim_t* icsim;
-  icsim_t* dcsim;
-  icsim_t* itlbsim;
-  icsim_t* dtlbsim;
+  // this constructor is used for each of the uts
+  processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx);
 
   friend class sim_t;
+  friend class mmu_t;
+  friend class htif_isasim_t;
 
-  static insn_func_t dispatch_table[DISPATCH_TABLE_SIZE];
-  reg_t dispatch(insn_t insn, reg_t pc);
-  static void initialize_dispatch_table();
-
-  #define DECLARE_INSN(name, m, o) reg_t insn_func_ ## name (insn_t, reg_t);
+  #define DECLARE_INSN(name, match, mask) \
+    reg_t rv32_ ## name(insn_t insn, reg_t pc); \
+    reg_t rv64_ ## name(insn_t insn, reg_t pc);
   #include "opcodes.h"
   #undef DECLARE_INSN
+
+  insn_func_t decode_insn(insn_t insn);
+  reg_t illegal_instruction(insn_t insn, reg_t pc);
 };
 
+#ifndef RISCV_ENABLE_RVC
+# define set_pc(x) \
+  do { if ((x) & 3) \
+         throw trap_instruction_address_misaligned; \
+       npc = (x); \
+     } while(0)
+#else
+# define set_pc(x) \
+  do { if ((x) & ((sr & SR_EC) ? 1 : 3)) \
+         throw trap_instruction_address_misaligned; \
+       npc = (x); \
+     } while(0)
+#endif
+
 #endif