Improve instruction fetch

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 942c491836255235261a03ddb7a8607f8e37e19b..d117ff1acbcc1d8988b68e412b373739efdbf6c4 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -1,55 +1,145 @@
+// See LICENSE for license details.
 #ifndef _RISCV_PROCESSOR_H
 #define _RISCV_PROCESSOR_H
 
-#include <cstring>
 #include "decode.h"
-#include "trap.h"
-#include "mmu.h"
+#include "config.h"
+#include <cstring>
+#include <vector>
+#include <map>
 
+class processor_t;
+class mmu_t;
+typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
 class sim_t;
+class trap_t;
+class extension_t;
+class disassembler_t;
 
-class processor_t
+struct insn_desc_t
 {
-public:
-  processor_t(sim_t* _sim, char* _mem, size_t _memsz);
-  void init(uint32_t _id);
-  void step(size_t n, bool noisy);
+  insn_bits_t match;
+  insn_bits_t mask;
+  insn_func_t rv32;
+  insn_func_t rv64;
+};
 
-private:
-  sim_t* sim;
+struct commit_log_reg_t
+{
+  reg_t addr;
+  reg_t data;
+};
 
-  // architected state
-  reg_t R[NGPR];
-  freg_t FR[NFPR];
+// architectural state of a RISC-V hart
+struct state_t
+{
+  void reset();
 
-  // privileged control registers
   reg_t pc;
-  reg_t epc;
-  reg_t badvaddr;
-  reg_t ebase;
-  uint32_t id;
-  uint32_t sr;
+  regfile_t<reg_t, NXPR, true> XPR;
+  regfile_t<freg_t, NFPR, false> FPR;
 
-  // unprivileged control registers
-  uint32_t tid;
-  uint32_t fsr;
+  // control and status registers
+  reg_t mstatus;
+  reg_t mepc;
+  reg_t mbadaddr;
+  reg_t mtimecmp;
+  reg_t mscratch;
+  reg_t mcause;
+  reg_t minstret;
+  reg_t mie;
+  reg_t mip;
+  reg_t sepc;
+  reg_t sbadaddr;
+  reg_t sscratch;
+  reg_t stvec;
+  reg_t sptbr;
+  reg_t scause;
+  reg_t sutime_delta;
+  reg_t suinstret_delta;
+  reg_t tohost;
+  reg_t fromhost;
+  uint32_t fflags;
+  uint32_t frm;
+  bool serialized; // whether timer CSRs are in a well-defined state
 
-  // 32-bit or 64-bit mode (redundant with sr)
-  int gprlen;
+  reg_t load_reservation;
 
-  // shared memory
-  mmu_t mmu;
+#ifdef RISCV_ENABLE_COMMITLOG
+  commit_log_reg_t log_reg_write;
+#endif
+};
 
-  // counters
-  reg_t counters[32];
+// this class represents one processor in a RISC-V machine.
+class processor_t
+{
+public:
+  processor_t(const char* isa, sim_t* sim, uint32_t id);
+  ~processor_t();
+
+  void set_debug(bool value);
+  void set_histogram(bool value);
+  void reset(bool value);
+  void step(size_t n); // run for n cycles
+  void deliver_ipi(); // register an interprocessor interrupt
+  bool running() { return run; }
+  void set_csr(int which, reg_t val);
+  void raise_interrupt(reg_t which);
+  reg_t get_csr(int which);
+  mmu_t* get_mmu() { return mmu; }
+  state_t* get_state() { return &state; }
+  extension_t* get_extension() { return ext; }
+  bool supports_extension(unsigned char ext) {
+    return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
+  }
+  void push_privilege_stack();
+  void pop_privilege_stack();
+  void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
+  void update_histogram(size_t pc);
+
+  void register_insn(insn_desc_t);
+  void register_extension(extension_t*);
 
-  // functions
-  void set_sr(uint32_t val);
-  void set_fsr(uint32_t val);
-  void take_trap(trap_t t, bool noisy);
-  void disasm(insn_t insn, reg_t pc);
+private:
+  sim_t* sim;
+  mmu_t* mmu; // main memory is always accessed via the mmu
+  extension_t* ext;
+  disassembler_t* disassembler;
+  state_t state;
+  reg_t cpuid;
+  uint32_t id;
+  int max_xlen;
+  int xlen;
+  bool run; // !reset
+  bool debug;
+  bool histogram_enabled;
+
+  std::vector<insn_desc_t> instructions;
+  std::map<size_t,size_t> pc_histogram;
+
+  static const size_t OPCODE_CACHE_SIZE = 8191;
+  insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
+
+  void check_timer();
+  void take_interrupt(); // take a trap if any interrupts are pending
+  void take_trap(trap_t& t, reg_t epc); // take an exception
+  void disasm(insn_t insn); // disassemble and print an instruction
 
   friend class sim_t;
+  friend class mmu_t;
+  friend class extension_t;
+
+  void parse_isa_string(const char* isa);
+  void build_opcode_map();
+  void register_base_instructions();
+  insn_func_t decode_insn(insn_t insn);
 };
 
+reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
+
+#define REGISTER_INSN(proc, name, match, mask) \
+  extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
+  extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
+  proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
+
 #endif