Add writing to DCSR, DPC, DSCRATCH.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 13c4cbbcf91c7a803fbf4fc4c299a0b7e30193c9..e0142995c1c09d8eb5ae6ce829738d4e8ec1dbeb 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -31,6 +31,19 @@ struct commit_log_reg_t
   reg_t data;
 };
 
+typedef struct
+{
+  uint8_t prv;
+  bool step;
+  bool debugint;
+  bool ebreakm;
+  bool ebreakh;
+  bool ebreaks;
+  bool ebreaku;
+  bool halt;
+  uint8_t cause;
+} dcsr_t;
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -41,25 +54,30 @@ struct state_t
   regfile_t<freg_t, NFPR, false> FPR;
 
   // control and status registers
+  reg_t prv;
   reg_t mstatus;
   reg_t mepc;
   reg_t mbadaddr;
-  reg_t mtimecmp;
   reg_t mscratch;
+  reg_t mtvec;
   reg_t mcause;
   reg_t minstret;
   reg_t mie;
   reg_t mip;
+  reg_t medeleg;
+  reg_t mideleg;
+  reg_t mucounteren;
+  reg_t mscounteren;
   reg_t sepc;
   reg_t sbadaddr;
   reg_t sscratch;
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
-  reg_t sutime_delta;
-  reg_t suinstret_delta;
-  reg_t tohost;
-  reg_t fromhost;
+  reg_t dpc;
+  reg_t dscratch;
+  dcsr_t dcsr;
+
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
@@ -72,6 +90,15 @@ struct state_t
 #endif
 };
 
+typedef enum {
+      HR_NONE,
+      HR_STEPPED,       // A single step was completed
+      HR_SWBP,          // sbreak was executed
+      HR_INTERRUPT,     // Execution interrupted by debugger
+      HR_CMDLINE,       // Command line requested that the processor start halted
+      HR_ATTACHED       // Halted because a debugger attached
+} halt_reason_t;
+
 // this class represents one processor in a RISC-V machine.
 class processor_t : public abstract_device_t
 {
@@ -80,6 +107,8 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
+  void set_halted(bool value, halt_reason_t reason);
+  void set_single_step(bool value);
   void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
@@ -92,10 +121,9 @@ public:
   extension_t* get_extension() { return ext; }
   bool supports_extension(unsigned char ext) {
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
-    return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
+    return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
   }
-  void push_privilege_stack();
-  void pop_privilege_stack();
+  void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
   void update_histogram(reg_t pc);
 
@@ -112,13 +140,20 @@ private:
   extension_t* ext;
   disassembler_t* disassembler;
   state_t state;
-  reg_t cpuid;
   uint32_t id;
-  int max_xlen;
-  int xlen;
-  std::string isa;
+  unsigned max_xlen;
+  unsigned xlen;
+  reg_t isa;
+  std::string isa_string;
   bool run; // !reset
+  // When true, display disassembly of each instruction that's executed.
   bool debug;
+  // TODO: Should this just be rolled into `run`?
+  bool halted;  // When true, no instructions are executed.
+  halt_reason_t halt_reason;        // Why is halted true?
+  // When true, execute exactly one instruction (even if halted is true), then
+  // set halted to true and single_step to false.
+  bool single_step;
   bool histogram_enabled;
 
   std::vector<insn_desc_t> instructions;
@@ -134,7 +169,9 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
+  friend class rtc_t;
   friend class extension_t;
+  friend class gdbserver_t;
 
   void parse_isa_string(const char* isa);
   void build_opcode_map();