Add writing to DCSR, DPC, DSCRATCH.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e654c0fea2b8aec2830ba060c73e87a02eb47950..e0142995c1c09d8eb5ae6ce829738d4e8ec1dbeb 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -31,6 +31,19 @@ struct commit_log_reg_t
   reg_t data;
 };
 
+typedef struct
+{
+  uint8_t prv;
+  bool step;
+  bool debugint;
+  bool ebreakm;
+  bool ebreakh;
+  bool ebreaks;
+  bool ebreaku;
+  bool halt;
+  uint8_t cause;
+} dcsr_t;
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -61,6 +74,10 @@ struct state_t
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
+  reg_t dpc;
+  reg_t dscratch;
+  dcsr_t dcsr;
+
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
@@ -73,6 +90,15 @@ struct state_t
 #endif
 };
 
+typedef enum {
+      HR_NONE,
+      HR_STEPPED,       // A single step was completed
+      HR_SWBP,          // sbreak was executed
+      HR_INTERRUPT,     // Execution interrupted by debugger
+      HR_CMDLINE,       // Command line requested that the processor start halted
+      HR_ATTACHED       // Halted because a debugger attached
+} halt_reason_t;
+
 // this class represents one processor in a RISC-V machine.
 class processor_t : public abstract_device_t
 {
@@ -81,7 +107,7 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
-  void set_halted(bool value);
+  void set_halted(bool value, halt_reason_t reason);
   void set_single_step(bool value);
   void set_histogram(bool value);
   void reset(bool value);
@@ -124,6 +150,7 @@ private:
   bool debug;
   // TODO: Should this just be rolled into `run`?
   bool halted;  // When true, no instructions are executed.
+  halt_reason_t halt_reason;        // Why is halted true?
   // When true, execute exactly one instruction (even if halted is true), then
   // set halted to true and single_step to false.
   bool single_step;