[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e92d093fc1dea25b455ffbfab2ded75e49d49ca4..f269fa04ce96847bdb8e08c50b179258e1de18d8 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -34,12 +34,14 @@ private:
   reg_t evec;
   reg_t tohost;
   reg_t fromhost;
+  reg_t vecbanks;
   reg_t pcr_k0;
   reg_t pcr_k1;
   uint32_t id;
   uint32_t sr;
   uint32_t count;
   uint32_t compare;
+  uint32_t vecbanks_count;
 
   // unprivileged control registers
   uint32_t fsr;