add load-reserved/store-conditional instructions

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 168f95ec0411f515d7e03a2154d0760d5d787e3d..f3b2f62cd69443d1eaa0c3cfd1fbb351143ebb3c 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_PROCESSOR_H
 #define _RISCV_PROCESSOR_H
 
@@ -25,7 +27,9 @@ public:
   void deliver_ipi(); // register an interprocessor interrupt
   bool running() { return run; }
   void set_pcr(int which, reg_t val);
+  void set_interrupt(int which, bool on);
   reg_t get_pcr(int which);
+  mmu_t* get_mmu() { return &mmu; }
 
 private:
   sim_t& sim;
@@ -35,8 +39,6 @@ private:
   regfile_t<reg_t, NXPR, true> XPR;
   regfile_t<freg_t, NFPR, false> FPR;
   reg_t pc;
-
-  // counters
   reg_t cycle;
 
   // privileged control registers
@@ -48,16 +50,12 @@ private:
   reg_t cause;
   reg_t tohost;
   reg_t fromhost;
-  uint32_t interrupts_pending;
   uint32_t id;
   uint32_t sr; // only modify the status register using set_pcr()
   uint32_t fsr;
   uint32_t count;
   uint32_t compare;
 
-  // # of bits in an XPR (32 or 64). (redundant with sr)
-  int xprlen;
-
   bool run; // !reset
 
   // functions