add load-reserved/store-conditional instructions

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index a6751410be8e12c10d1ba973b23d71131f407e3e..f3b2f62cd69443d1eaa0c3cfd1fbb351143ebb3c 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -1,9 +1,12 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_PROCESSOR_H
 #define _RISCV_PROCESSOR_H
 
 #include "decode.h"
 #include <cstring>
 #include "trap.h"
+#include "config.h"
 
 #define MAX_UTS 2048
 
@@ -19,19 +22,23 @@ public:
   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
   ~processor_t();
 
+  void reset(bool value);
   void step(size_t n, bool noisy); // run for n cycles
   void deliver_ipi(); // register an interprocessor interrupt
+  bool running() { return run; }
+  void set_pcr(int which, reg_t val);
+  void set_interrupt(int which, bool on);
+  reg_t get_pcr(int which);
+  mmu_t* get_mmu() { return &mmu; }
 
 private:
   sim_t& sim;
   mmu_t& mmu; // main memory is always accessed via the mmu
 
   // user-visible architected state
-  reg_t XPR[NXPR];
-  freg_t FPR[NFPR];
+  regfile_t<reg_t, NXPR, true> XPR;
+  regfile_t<freg_t, NFPR, false> FPR;
   reg_t pc;
-
-  // counters
   reg_t cycle;
 
   // privileged control registers
@@ -40,26 +47,21 @@ private:
   reg_t evec;
   reg_t pcr_k0;
   reg_t pcr_k1;
-  uint32_t cause;
-  uint32_t interrupts_pending;
+  reg_t cause;
+  reg_t tohost;
+  reg_t fromhost;
   uint32_t id;
-  uint32_t sr; // only modify the status register using set_sr()
+  uint32_t sr; // only modify the status register using set_pcr()
   uint32_t fsr;
   uint32_t count;
   uint32_t compare;
 
-  // # of bits in an XPR (32 or 64). (redundant with sr)
-  int xprlen;
-
-  // is this processor running? (deliver_ipi() sets this)
-  bool run;
+  bool run; // !reset
 
   // functions
-  void reset(); // resets architected state; halts processor if it was running
   void take_interrupt(); // take a trap if any interrupts are pending
-  void set_sr(uint32_t val); // set the status register
   void set_fsr(uint32_t val); // set the floating-point status register
-  void take_trap(trap_t t, bool noisy); // take an exception
+  void take_trap(reg_t t, bool noisy); // take an exception
   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
 
   // vector stuff
@@ -83,8 +85,23 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
+  friend class htif_isasim_t;
 
   #include "dispatch.h"
 };
 
+#ifndef RISCV_ENABLE_RVC
+# define set_pc(x) \
+  do { if((x) & (sizeof(insn_t)-1)) \
+       { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+       npc = (x); \
+     } while(0)
+#else
+# define set_pc(x) \
+  do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
+       { badvaddr = (x); throw trap_instruction_address_misaligned; } \
+       npc = (x); \
+     } while(0)
+#endif
+
 #endif