Add debug_module bus device.

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index c7d84f794559b48dc7ab76c5b2a93b909f3966b4..279fbde8130e17656bf7a29a18e5ba2a23a17831 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -25,6 +25,7 @@ riscv_hdrs = \
        insn_template.h \
        mulhi.h \
        gdbserver.h \
+       debug_module.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
@@ -47,6 +48,7 @@ riscv_srcs = \
        rom.cc \
        rtc.cc \
        gdbserver.cc \
+       debug_module.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =