Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 17479dce558847a06d7e9fdb8cdc60ea21b55965..05e316a438ad4dd68e1e9f2646328afc1d5c1758 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -23,8 +23,9 @@ riscv_hdrs = \
        rocc.h \
        insn_template.h \
        mulhi.h \
-       gdbserver.h \
        debug_module.h \
+       remote_bitbang.h \
+       jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
@@ -44,9 +45,10 @@ riscv_srcs = \
        regnames.cc \
        devices.cc \
        rom.cc \
-       rtc.cc \
-       gdbserver.cc \
+       clint.cc \
        debug_module.cc \
+       remote_bitbang.cc \
+       jtag_dtm.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -180,9 +182,9 @@ riscv_insn_list = \
        fmul_d \
        fmul_s \
        fmv_d_x \
-       fmv_s_x \
+       fmv_w_x \
        fmv_x_d \
-       fmv_x_s \
+       fmv_x_w \
        fnmadd_d \
        fnmadd_s \
        fnmsub_d \