riscv_install_prog_srcs = \
riscv_hdrs = \
- htif.h \
common.h \
decode.h \
devices.h \
rocc.h \
insn_template.h \
mulhi.h \
- gdbserver.h \
debug_module.h \
+ remote_bitbang.h \
+ jtag_dtm.h \
riscv_precompiled_hdrs = \
insn_template.h \
riscv_srcs = \
- htif.cc \
processor.cc \
execute.cc \
sim.cc \
regnames.cc \
devices.cc \
rom.cc \
- rtc.cc \
- gdbserver.cc \
+ clint.cc \
debug_module.cc \
+ remote_bitbang.cc \
+ jtag_dtm.cc \
$(riscv_gen_srcs) \
riscv_test_srcs =
divu \
divuw \
divw \
+ dret \
ebreak \
ecall \
fadd_d \
fmul_d \
fmul_s \
fmv_d_x \
- fmv_s_x \
+ fmv_w_x \
fmv_x_d \
- fmv_x_s \
+ fmv_x_w \
fnmadd_d \
fnmadd_s \
fnmsub_d \
sc_d \
sc_w \
sd \
- sfence_vm \
+ sfence_vma \
sh \
sll \
slli \