Factor out the dummy RoCC accelerator

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index ada62d5c0c85fbc7cc778d949b50b90a8ee5d758..0d5869dae2a290c409c64c8d3490e33bae74fe7a 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1,23 +1,58 @@
-riscv_subproject_deps =
+get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
+get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
+
+riscv_subproject_deps = \
+       softfloat \
+
+riscv_install_prog_srcs = \
 
 riscv_hdrs = \
+       htif.h \
        common.h \
        decode.h \
-       execute.h \
-       load_elf.h \
        mmu.h \
        processor.h \
        sim.h \
        trap.h \
-       insns/*.h \
+       encoding.h \
+       cachesim.h \
+       memtracer.h \
+       extension.h \
+       rocc.h \
+       insn_template.h \
+       mulhi.h \
+
+riscv_precompiled_hdrs = \
+       insn_template.h \
 
 riscv_srcs = \
-       load_elf.cc \
+       htif.cc \
        processor.cc \
        sim.cc \
+       interactive.cc \
        trap.cc \
+       cachesim.cc \
+       mmu.cc \
+       disasm.cc \
+       extension.cc \
+       rocc.cc \
+       regnames.cc \
+       $(riscv_gen_srcs) \
 
 riscv_test_srcs =
 
-riscv_install_prog_srcs = \
-       riscv-isa-run.cc \
+riscv_gen_hdrs = \
+  icache.h \
+
+riscv_gen_srcs = \
+       $(addsuffix .cc, $(call get_insn_list,$(src_dir)/riscv/encoding.h))
+
+icache.h:
+       $(src_dir)/riscv/gen_icache 1024 > $@.tmp
+       mv $@.tmp $@
+
+$(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
+       sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
+
+riscv_junk = \
+       $(riscv_gen_srcs) \