Add dret.

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 757b3f091b8cb07cf6e1f983ee053b3952b08f5b..65f8c99a84936ccc0cc053be38884eaf6552cbb9 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -11,7 +11,6 @@ riscv_hdrs = \
        common.h \
        decode.h \
        devices.h \
-       devicetree.h \
        disasm.h \
        mmu.h \
        processor.h \
@@ -25,6 +24,8 @@ riscv_hdrs = \
        rocc.h \
        insn_template.h \
        mulhi.h \
+       gdbserver.h \
+       debug_module.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
@@ -46,6 +47,8 @@ riscv_srcs = \
        devices.cc \
        rom.cc \
        rtc.cc \
+       gdbserver.cc \
+       debug_module.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -131,6 +134,7 @@ riscv_insn_list = \
        divu \
        divuw \
        divw \
+       dret \
        ebreak \
        ecall \
        fadd_d \