add I$/D$/L2$ simulators

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 50dc76a746a0cddc85e2e4c3407e4d9d9a8c5497..bf6e07ab6f637ba067a5e7bc84dfc690b222577c 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -13,6 +13,8 @@ riscv_hdrs = \
        opcodes.h \
        insn_header.h \
        dispatch.h \
+       cachesim.h \
+       memtracer.h \
 
 NDISPATCH := 10
 DISPATCH_SRCS := \
@@ -40,8 +42,9 @@ riscv_srcs = \
        sim.cc \
        interactive.cc \
        trap.cc \
-       icsim.cc \
+       cachesim.cc \
        mmu.cc \
+       disasm.cc \
        $(DISPATCH_SRCS) \
 
 riscv_test_srcs =