add I$/D$/L2$ simulators

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 6d55c8033876d848c66c85cfd0db6f511d10caa3..bf6e07ab6f637ba067a5e7bc84dfc690b222577c 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -3,21 +3,49 @@ riscv_subproject_deps = \
        softfloat \
 
 riscv_hdrs = \
-    applink.h \
+       htif.h \
        common.h \
        decode.h \
-       execute.h \
        mmu.h \
        processor.h \
        sim.h \
        trap.h \
-       insns/*.h \
+       opcodes.h \
+       insn_header.h \
+       dispatch.h \
+       cachesim.h \
+       memtracer.h \
+
+NDISPATCH := 10
+DISPATCH_SRCS := \
+       dispatch0.cc \
+       dispatch1.cc \
+       dispatch2.cc \
+       dispatch3.cc \
+       dispatch4.cc \
+       dispatch5.cc \
+       dispatch6.cc \
+       dispatch7.cc \
+       dispatch8.cc \
+       dispatch9.cc \
+       dispatch10.cc \
+
+$(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
+       $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
+
+$(src_dir)/riscv/dispatch.h: %.h: dispatch
+       $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
 
 riscv_srcs = \
-    applink.cc \
+       htif.cc \
        processor.cc \
        sim.cc \
+       interactive.cc \
        trap.cc \
+       cachesim.cc \
+       mmu.cc \
+       disasm.cc \
+       $(DISPATCH_SRCS) \
 
 riscv_test_srcs =