add I$/D$/L2$ simulators

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index f6553c169a8cd60b011849dde769c6e8e6bf0f2b..bf6e07ab6f637ba067a5e7bc84dfc690b222577c 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -2,10 +2,8 @@ riscv_subproject_deps = \
        softfloat_riscv \
        softfloat \
 
-riscv_insn_hdrs := $(notdir $(wildcard $(src_dir)/riscv/insns/*.h))
-
 riscv_hdrs = \
-       applink.h \
+       htif.h \
        common.h \
        decode.h \
        mmu.h \
@@ -14,24 +12,40 @@ riscv_hdrs = \
        trap.h \
        opcodes.h \
        insn_header.h \
-       insn_footer.h \
+       dispatch.h \
+       cachesim.h \
+       memtracer.h \
+
+NDISPATCH := 10
+DISPATCH_SRCS := \
+       dispatch0.cc \
+       dispatch1.cc \
+       dispatch2.cc \
+       dispatch3.cc \
+       dispatch4.cc \
+       dispatch5.cc \
+       dispatch6.cc \
+       dispatch7.cc \
+       dispatch8.cc \
+       dispatch9.cc \
+       dispatch10.cc \
+
+$(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
+       $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
 
-$(patsubst %.h, %.cc, $(riscv_insn_hdrs)): %.cc: insns/%.h $(riscv_hdrs)
-       @echo \#define FUNC insn_func_$(@:.cc=)      > $@
-       @echo \#define OPCODE_MASK MASK_$(@:.cc=)   >> $@
-       @echo \#define OPCODE_MATCH MATCH_$(@:.cc=) >> $@
-       @cat $(src_dir)/riscv/insn_header.h         >> $@
-       @cat $<                                     >> $@
-       @cat $(src_dir)/riscv/insn_footer.h         >> $@
+$(src_dir)/riscv/dispatch.h: %.h: dispatch
+       $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
 
 riscv_srcs = \
-       applink.cc \
+       htif.cc \
        processor.cc \
        sim.cc \
+       interactive.cc \
        trap.cc \
-       icsim.cc \
+       cachesim.cc \
        mmu.cc \
-       $(patsubst %.h, %.cc, $(riscv_insn_hdrs)) \
+       disasm.cc \
+       $(DISPATCH_SRCS) \
 
 riscv_test_srcs =